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october 2012 i ? 2012 microsemi corporation smartfusion2 system-on-chip fpgas microsemi?s smartfusion ? 2 soc fpgas integrate fourth generat ion flash-based fpga fabric, an arm ? cortex?-m3 processor, and high performance communications interfaces on a single chip . the smartfusion2 family is the industry?s lowest power, most reliable and highest security programmable logic solution. this ne xt generation smartfusion2 archit ecture offers up to 3.6x gat e count implemented with 4-input look-up tabl e (lut) fabric with carry chains, giving 2x performance, and includes multiple embed ded memory options and math blocks for digital signal processing (dsp). the 166 mhz arm cortex-m3 processor is enhanced with an embedded trace macrocell (etm), memory prot ection unit (mpu), 8 kbyte instruction ca che, and additional peripherals including controller area network (can), gigabit et hernet, and high speed universal serial bus (usb). high speed serial interfaces includ e peripheral component interconnect express (pci e), 10 gbps attachment unit interface ( xaui) / xgmii extended sublayer (xgxs) + native serialization/deserialization (serde s) communication, while double data rate 2 (ddr2)/ddr3 memory controllers provide high speed memory interfaces. smartfusion2 family reliability ? single event upset (seu) immune ? zero fit fpga configuration cells ? single error correct double error detect (secded) protection on the following: ? ethernet buffers ? can message buffers ? cortex-m3 embedded scratch pad memory (esrams) ? usb buffers ?pcie buffer ? ddr memory controllers with optional secded modes ? buffers implemented with seu resistant latches on the following: ? ddr bridges (mss, mddr, fddr) ? instruction cache ? mmuart fifos ? spi fifos ? nvm integrity check at power-up and on-demand ? no external configuration memory required?instant- on, retains configuration when powered off security ? design security features (available on all devices) ? intellectual property (ip) protection via unique security features and use models new to the pld industry ? encrypted user key and bitstream loading, enabling programming in less-trusted locations ? supply-chain assurance device certificate ? enhanced anti-tamper features ? zeroization ? data security features (available on premium devices) ? non-deterministic random bit generator (nrbg) ? user cryptographic serv ices (aes-256, sha-256, elliptical curve cryptographic (ecc) engine) ? user physically unclonable function (puf) key enrollment and regeneration ? cri pass-through dpa patent portfolio license ? hardware firewalls protecting microcontroller subsystem (mss) memories low power ? low static and dynamic power ? flash*freeze mode for fabric ? for the m2s050 device: ? < 1 mw in flash*freeze mode ? 10 mw in standby mode ? based on 65 nm nonvolatile flash process high-performance fpga ? efficient 4-input luts with carry chains for high performance and low power ? up to 236 blocks of dual-p ort 18 kbit sram (large sram) with 400 mhz synchronous performance (x18, x9, x4, x2, x1) ? up to 240 blocks of three- port 1 kbit sram with 2 read ports and 1 write port (micro sram) ? high performance dsp signal processing ? up to 240 fast math blocks with 18 x 18 signed multiplication, 17 x 17 unsigned multiplication and 44-bit accumulator revision 0
smartfusion2 system-on-chip fpgas ii revision 0 microcontroller subsystem (mss) ? hard 166 mhz 32-bit arm cortex-m3 processor ? 1.25 dmips/mhz ? 8 kbyte instruction cache ? embedded trace macrocell (etm) ? memory protection unit (mpu) ? single cycle multiplication, hardware divide ? jtag debug (4 wires), serial wire debug (swd, 2 wires), and serial wire viewer (swv) interfaces ? 64 kb embedded sram (esram) ? up to 512 kb embedded nonvolatile memory (envm) ? triple speed ethernet (tse) 10/100/1000 mbps mac ? usb 2.0 high speed on-the-go (otg) controller with ulpi interface ? can controller, 2.0b compliant, conforms to iso11898-1, 32 transmit and 32 receive buffers ? two each: spi, i 2 c, multi-mode uarts (mmuart) peripherals ? hardware based watchdog timer ? 1 general purpose 64-bit (or two 32-bit) timer(s) ? real-time calendar/counter (rtc) ? ddr bridge (4 port data r/w buffering bridge to ddr memory) with 64-bit axi interface ? non-blocking, multi-layer ahb bus matrix allowing multi-master scheme supporting 10 masters and 7 slaves ? two ahb/apb interfaces to fpga fabric (master/slave capable) ? two dma controllers to offload data transactions from the cortex-m3 processor ? 8-channel peripheral dma (pdma) for data transfer between mss peripherals and memory ? high performance dma (hpdma) for data transfer between esram and ddr memories clocking resources ? clock sources ? up to two high precision 32 khz to 20 mhz main crystal oscillator ? 1 mhz embedded rc oscillator ? 50 mhz embedded rc oscillator ? up to 8 clock conditioning circuits (cccs) with up to 8 integrated analog plls ? output clock with 8 output phases and 45 phase difference (multiply/divide, and delay capabilities) ? frequency: input 1 to 200 mhz, output 20 to 400 mhz high speed serial interfaces ? up to 16 serdes lanes, each supporting: ? xgxs/xaui extension (to implement a 10 gbps (xgmii) ethernet phy interface) ? native serdes interface fa cilitates implementation of serial rapidio in fabric or an sgmii interface to the ethernet mac in mss ? pci express (pcie) endpoint controller x1, x2, x4 lane pci ex press core with 16-bit pipe interface (gen1/gen2) 256 bytes maximum payload size 64-/32-bit axi/ahb master and slave interfaces to the application layer high speed memory interfaces ? up to 2 high speed ddrx memory controllers ? mss ddr (mddr) and fabric ddr (fddr) controllers ? supports lpddr/ddr2/ddr3 ? maximum 333 mhz clock rate ? secded enable/disable feature ? supports various dram bus width modes, x16, x18, x32, x36 ? supports command reordering to optimize memory efficiency ? supports data reordering, returning critical word first for each command ? sdram support operating voltage and i/os ? 1.2 v core voltage ? multi-standard user i/os (msio/msiod) ? lvttl/lvcmos 3.3 v ? lvcmos 1.2 v, 1.5 v, 1.8 v, 2.5 v ? ddr (sstl2_1, sstl2_2) ? ddr2 (sstl18_1, sstl18_2) ? lvds, mlvds, mini-lvd s, rsds differential standards ?pci ? lvpecl (receiver only) ? ddr i/os (ddrio) ? ddr, ddr2, ddr3, lpddr, sstl2, sstl18, hstl ? lvcmos 1.2v, 1.5v, 1.8v, 2.5v
smartfusion2 system-on-chip fpgas revision 0 iii smartfusion2 soc fpga block diagram acronyms aes advanced encryption standard mddr ddr2/3 controller in mss ahb advanced high-performance bus mmuart multi-mode uart apb advanced peripheral bus mpu memory protection unit axi advanced extensible interf ace mss microcontroller subsystem comm_blk communication block secded single error correct double error detect ddr double data rate seu single event upset dpa differential power analysis sha secure hashing algorithm ecc elliptical curve cryptography smc_fic soft memory controller edac error detection and correction tse triple speed ethernet (10/100/1000 mbps) etm embedded trace macrocell ulpi utmi + low pin interface fddr ddr2/3 controller in fpga fabric utmi usb 2.0 transceiver macrocell interface fic fabric interface controller wdt watchdog timer fiic fabric interface interrupt controller xaui 10 gbps attachment unit interface hs usb otg high speed usb 2.0 on-the-go xg mii 10 gigabit media independent interface iap in-application programming xgxs xgmii extended sublayer macc multiply-accumulate fpga fabric micro sram (64x18) micro sram (64x18) large sram (1024x18) large sram (1024x18) math block macc (18x18) math block macc (18x18) ddr bridge mss ddr controller + phy serial controller 0 (pcie, xaui/xgxs) + native serdes instruction cache esram tse mac hpdma fic_1 fic_0 comm_blk oscs plls sysreg envm hs usb otg ulpi pdma apb sram-puf jtag i/o ddr user i/o ddr user i/o serial 1 i/o serial 0 i/o spi i/o multi-standard user i/o (miso) multi-standard user i/o (miso) sha256 aes256 in-application programming nrbg ecc flash*freeze fiic rtc wdt can spi x 2 mmuart x 2 i 2 c x 2 timer x 2 ahb bus matrix (abm) mpu arm cortex -m3 microcontroller subsystem (mss) system controller etm s d ahb axi/ahb/xgxs cong fabric ddr controller + phy axi/ahb cong serial controller 1 (pcie, xaui/xgxs) + native serdes axi/ahb/xgxs cong smc_fic axi/ahb cong ahb ahb interupts i f p g a fabric micro andard user i /o ( mi so) multi-standard user i/o (miso) standard cell / seu immune flash based / seu immune
smartfusion2 system-on-chip fpgas iv revision 0 i/os per package table 1 ? smartfusion2 soc fpga product family features m2s005 m2s010 m2s025 m2s050 m2s080 m2s120 fpga logic modules (4-input lut) 4,956 9,744 23,988 48,672 82,232 120,348 lsram 18k blocks 10 21 31 69 160 236 usram 1k blocks 11 22 34 72 160 240 total ram (bits) 191k 400k 592k 1,314k 3,040k 4,500k math blocks 11 22 34 72 160 240 plls and cccs 224688 mss cortex-m3 processor + instruction cache yes yes yes yes yes yes envm (bytes) 128k 256k 256k 256k 512k 512k esram (bytes) 64k 64k 64k 64k 64k 64k esram (bytes non-secded) 80k 80k 80k 80k 80k 80k can 2.0 a and b 111111 triple speed ethernet 10/100/1000 111111 usb 2.0 high speed on-the-go 111111 multi-mode uart 222222 spi 222222 i2c 222222 timer 222222 memory, serial i/f ddr controllers 1x18 1x18 1x18 2x36 2x36 2x36 serdes channels 0 4 4 8 8 16 pcie endpoint 4 0 1 1 2 2 4 user i/o 3.3 v multi-standard user i/os (msios) 123 123 159 139 292 292 msiod i/os 28 40 40 62 106 106 ddrio i/os 66 70 90 176 176 176 total user i/os 217 233 289 377 574 574 serdes i/os 0 16 16 32 64 64 total user i/os + serdes i/os 217 249 305 409 638 638 table 2 ? i/os per package and package options package options vf400 fg484 fg896 fc1152 pin count 400 484 896 1,152 ball pitch (mm) 0.8 1.0 1.0 1.0 length width (mm\mm) 17 17 23 23 31 31 35 35 i/os xcvrs i/os xcvrs i/os xcvrs i/os xcvrs m2s005 160 ? 217 ? ? ? ? ? m2s010 160 4 233 4 ? ? ? ? m2s025 160 4 267 4 ? ? ? ? m2s050 160 4 267 4 377 8 ? ? m2s080 ? ? ? ? ? ? 574 8 m2s120 ? ? ? ? ? ? 574 16 note: user i/os do not include the serdes and jtag pins.
smartfusion2 system-on-chip fpgas revision 0 v smartfusion2 ordering information . speed grade blank = tbd t = with transceiver blank = no transceiver 1 = tbd m2s050 t fg _ part number (digits indicate thousands of luts) transceiver s = design security blank = data and design security s security 1 package type vf = very fine pitch ball grid array (0.8 mm pitch) 144 i y package lead count g lead-free packaging application (temperature range) blank = commercial (0c to +85c ambient temperature) i = industrial ( ? 40c to +100c ambient temperature) blank = standard packaging g = rohs-compliant es = engineering sample (room temperature only) m2s005 m2s010 m2s025 m2s050 m2s080 m2s120 fg = fine pitch ball grid array (1.0 mm pitch) security feature y = device includes license to implement ip based on the cryptography research, inc. (cri) patent portfolio
smartfusion2 system-on-chip fpgas vi revision 0 smartfusion2 valid part numbers smartfusion2 device status contact your local microsemi soc products gr oup representative for device availability: http://www.microsemi.com/soc/contact/default.aspx . table 3 ? smartfusion2 valid part numbers for devices with design security commercial industrial std. speed grade ?1 speed grade ?1 speed grade ?1 speed grade, data security m2s005-vf400 m2s005-1vf400 m2s005-1vf400i m2s005s-1vf400i m2s010-vf400 m2s010-1vf400 m2s010-1vf400i m2s010s-1vf400i m2s025-vf400 m2s025-1vf400 m2s025-1vf400i m2s025s-1vf400i m2s050-vf400 m2s050-1vf400 m2s050-1vf400i m2s050s-1vf400i m2s005-fg484 m2s005-1fg484 m2s 005-1fg484i m2s005s-1fg484i m2s010-fg484 m2s010-1fg484 m2s 010-1fg484i m2s010s-1fg484i m2s025-fg484 m2s025-1fg484 m2s 025-1fg484i m2s025s-1fg484i m2s050-fg484 m2s050-1fg484 m2s 050-1fg484i m2s050s-1fg484i m2s050-fg896 m2s050-1fg896 m2s 050-1fg896i m2s050s-1fg896i m2s080-fc1152 m2s080-1fc1152 m2s080-1fc1152i m2s080s-1fc1152i m2s120-fc1152 m2s120-1fc1152 m2s120-1fc1152i m2s120s-1fc1152i transceivers transceivers transceivers transceivers m2s010t-vf400 m2s010t-1vf400 m2s010t-1vf400i m2s010ts-1vf400i m2s025t-vf400 m2s025t-1vf400 m2s025t-1vf400i m2s025ts-1vf400i m2s050t-vf400 m2s050t-1vf400 m2s050t-1vf400i m2s050ts-1vf400i m2s010t-fg484 m2s010t-1fg484 m2 s010t-1fg484i m2s010ts-1fg484i m2s025t-fg484 m2s025t-1fg484 m2 s025t-1fg484i m2s025ts-1fg484i m2s050t-fg484 m2s050t-1fg484 m2 s050t-1fg484i m2s050ts-1fg484i m2s050t-fg896 m2s050t-1fg896 m2 s050t-1fg896i m2s050ts-1fg896i m2s080t-fc1152 m2s080t-1fc1152 m2s080t-1fc1152i m2s080ts-1fc1152i m2s120t-fc1152 m2s120t-1fc1152 m2s120t-1fc1152i m2s120ts-1fc1152i family devices status m2s050t advance
smartfusion2 system-on-chip fpgas revision 0 vii table of contents smartfusion2 device family overview reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 highest security devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 high performance fpga fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 microcontroller subsystem (mss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 clock sources: on-chip oscillators, plls, and cccs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 high speed serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 high speed memory interfaces: ddrx memory controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 smartfusion2 dc and switching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 average fabric temperature and voltage derating factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 logic module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 fpga fabric sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 clock conditioning circuits (ccc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 serial peripheral interface (spi) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 inter-integrated circuit (i 2 c) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85 smartfusion2 development tools libero soc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 softconsole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 softconsole user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 firmware catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 firmware catalog user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 soc fpga ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 smartfusion2 development kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 pin descriptions supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 dedicated global i/o naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 user i/o naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 multi-standard i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 microcontroller subsystem (mss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 multi-function i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 fg896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 datasheet information datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

revision 0 1-1 1 ? smartfusion2 device family overview microsemi?s smartfusion2 soc fpgas integrate four th generation flash-based fpga fabric, an arm cortex-m3 processor and high performance communications interfaces on a single chip. the smartfusion2 family is the industry?s lowest power , highest reliability and most secure programmable logic solution. this next generation smartfusion2 arch itecture offers up to 3.6x gate count implemented with 4-input look-up table (lut) fabric with carry chains, giving 2x performance, and includes multiple embedded memory options and math blocks for dsp. the 166 mhz arm cortex-m3 processor is enhanced with etm and 8 kbyte instruction cache, and additional peripherals including can, gigabit ethernet, and high speed usb. high speed serial interfaces enable pcie, xaui / xgxs + native serdes communication while ddr2/ddr3 memory cont rollers provide high speed memory interfaces. smartfusion2 chip layout mss ddr east ios 4 plls 4 plls west ios 3 plls column access fpga fabric serdes usram (1 kb) math blocks lsram (18 kb) serdes envm oscillators hvbias mss crystal fabric ddr
smartfusion2 device family overview 1-2 revision 0 reliability smartfusion2 flash-based fabric has zero fit configuration rate due to its single event upset (seu) immunity, which is critical in reliability applicatio ns. the flash fabric also has the advantage that no external configuration memory is required, making the device instant-on; it retains configuration when powered off. to complement this unique fpga capa bility, smartfusion2 adds reliability to many other aspects of the device. single error correct double e rror detect (secded) protection is implemented on the cortex-m3 embedded scratch pad memory, ethernet, can and usb buffers, and is optional on the ddr memory controllers. this means th at if a one-bit error is detect ed, it will be corrected. errors of more than one bit are detected only and not corrected. s ecded error signals are brought to the fpga fabric to allow the user to monito r the status of these pr otected internal memories. other areas of the architecture are implemented with la tches, which are not subject to seus. therefore, no correction is needed in these locations: ddr bridges (mss, mddr, fddr), instruction cache and mmuart, spi, and pcie fifos. highest security devices building further on the intrinsic security benefit s of flash nonvolatile memory technology, the smartfusion2 family incorporates essentially all the legacy security features that made the original smartfusion, fusion ? , igloo ? , and proasic ? 3 third-generation flash fpgas and csocs the gold standard for secure devices in the pld industry. in addition, the fourth-generation flash-based smartfusion2 soc fpgas add many unique design and data security features and use models new to the pld industry. design security vs. data security when classifying security attributes of programmable logic devices (plds), a us eful distinction is made between design security and data security. design security design security is protecting the intent of the owner of the design, such as keeping the design and associated bitstream keys confidential, preventin g design changes (insertion of trojan horses, for example), and controlling the number of copies made throughout the device life cycle. design security may also be known as intellectual property (ip) protection. it is one aspect of anti- tamper (at) protection. design security applies to the device from initial production, includes any updates such as in-the-field upgrades, and can include decommissioning of the device at the end of its life, if desired. good design security is a prerequisite for good data security. the following are the main design security features supported: ? user key and bitstream loading in less-trusted locations ? encrypted key loading using device-unique built-in factory key ? methods to verify devices are programmed corre ctly, even if done in less-trusted locations ? supply-chain assurances to eliminate counterfeiting ? differential power analysis (dpa) and enhanced anti-tamper features to address non-invasive, semi-invasive, and invasive attacks ? ability to zeroize (destroy) all sensitiv e stored data in the event of tampering ? the m2s080 and m2s120 also have the following features: ? elliptic curve cryptography (ecc) for securely loading user keys ? an sram-type physically unclonable functi on (sram-puf) for device authentication
smartfusion2 system-on-chip fpgas revision 0 1-3 data security data security is protecting the information the fpga is storing, processing, or communicating in its role in the end application. if, for example, the configur ed design is implementing the key management and encryption portion of a secure milita ry radio, data security could entail encrypting and authenticating the radio traffic, and protecting the asso ciated application-level cryptographic keys. data security is closely related to the terms information assu rance (ia) and information security. all smartfusion2 devices incorporate enhanced design security, making them the most secure programmable logic devices ever made. select sm artfusion2 models also include an advanced set of on-chip data security features that make designing secure information assurance applications easier and better than ever before. the following are the main data security features supported: ? non-deterministic random bi t generator (nrbg) service ? user cryptographic services (e.g ., aes-128/-256, sha-256, and hmac) ? hardware firewalls protecting mss memories ? cryptography research inc. (cri) pass-thr ough differential power analysis (dpa) patent portfolio license ? the m2s080 and m2s120 also have the following features: ? elliptic curve cryptography (ecc) cryptographic computation services ? user puf key enrollment and regeneratio n for advanced design and data security applications low power microsemi?s flash-based fpga fabric results in ex tremely low power design implementation with static power on the m2s050 device as low as 10 mw. flas h*freeze (f*f) technology provides an ultra-low power static mode (flash*freeze mode) for smartfus ion2 devices, with power less than 1 mw. f*f mode entry retains all the sram and register informa tion and the exit from f*f mode achieves rapid recovery to active mode. high performance fpga fabric built on 65 nm process technology, the smartfusion2 fpga fabric is composed of 4 building blocks: the logic module, the large sram, the micro sram and the math block. the logic module is the basic logic element and has advanced features: ? a fully permutable 4-input lut (look-up table) optimized for lowest power ? a dedicated carry chain based on carry look-ahead technique ? a separate flip-flop which can be used independently from the lut the 4-input look-up table can be configured either to implement any 4-input combinatorial function or to implement an arithmetic function where the lut outp ut is xored with carry input to generate the sum output. dual-port large sram (lsram) large sram (ram1kx18) is targeted for storing large memory for use with various operations. each lsram block can store up to 18,432 bits. each ram1kx18 block contains two independent data ports: port a and port b. the lsram is synchronous for both read and write operations. operations are triggered on the rising edge of the clock. the data output ports of the lsra m have pipeline registers which have control signals that are indep endent of the sram?s control signals. three-port micro sram (usram) micro sram (ram64x18) is the second type of sram which is embedded in the fabric of smartfusion2 devices. ram64x18 usram is a 3-port sram; it has two read ports (port a and port b) and one write
smartfusion2 device family overview 1-4 revision 0 port (port c). the two read ports are independent of each other and can perform read operations in both synchronous and asynchronous modes. the write port is always synchronous. the usram block is approximately 1 kb (1,152 bits) in size. these usram blocks are primarily targeted for building embedded fifos to be used by any embedded fabric masters. math blocks for dsp applications the fundamental building block in any digital signa l processing algorithm is the multiply-accumulate function. smartfusion2 implements a custom 18x 18 multiply-accumulate (18x18 macc) block for efficient implementation of complex dsp algorithms such as finite impulse response (fir) filters, infinite impulse response (iir) filters, and fast fourier transform (fft) for filtering and image processing applications. each math block has the following capabilities: ? supports 18x18 signed multiplications natively (a[17:0] x b[17:0]) ? supports dot product; the multiplier computes: (a[8:0] x b[17:9] + a[17:9] x b[8:0]) x 2 9 ? built-in addition, subtraction, and accumulation uni ts to combine multiplica tion results efficiently in addition to the basic macc function, dsp al gorithms typically need small amounts of ram for coefficients and larger rams for data storage. smartf usion2 micro rams are ideally suited to serve the needs of coefficient storage while the large rams are used for data storage. microcontroller subsystem (mss) the microcontroller subsystem (mss) contains a high-performance integrat ed cortex-m3 processor, running at up to 166 mhz. the mss contains an 8 kbyte instruction cache to pr ovide low latency access to internal envm and external ddr memory. the mss provides multiple interfacing options to the fpga fabric in order to facilitate tight integration between the m ss and user logic in the fabric. arm cortex-m3 processor the mss uses the latest revision (r2p1) of the arm cortex-m3 processor. microsemi?s implementation includes the optional embedded trace macrocell (e tm) features for easier development and debug and the memory protection unit (mpu) fo r real-time operati ng system support. cache controller in order to minimize latency for instruction fetc hes when executing firmware out of off-chip ddr or on-chip envm, an 8 kbyte, 4-way set associative instruction cache is implemented. this provides zero wait state access for cache hits and is shared by bot h i and d code buses of the cortex-m3 processor. in the event of cache misses, cache lines are filled, replacing existing cache entries based on a least recently used (lru) algorithm. there is a configurable option available to operat e the cache in a locked mode, whereby a fixed segment of code from either the ddr or envm is copied into the cache and lock ed there, so that it is not replaced when cache misses occur. this would be used for performance-critical code. it is also possible to disable the cache altogether, which is desirable in syst ems requiring very deterministic execution times. the cache is implemented with seu tolerant latches . ddr bridge the ddr bridge is a data bridge between four ahb bus masters and a single axi bus slave. the ddr bridge accumulates ahb writes into write combini ng buffers prior to bursting out to external ddr memory. the ddr bridge also includes read combining buffers, allowing ahb masters to efficiently read data from the external ddr memory from a local buff er. the ddr bridge optimizes reads and writes from multiple masters to a single external ddr memory. data coherency rules between the four masters and
smartfusion2 system-on-chip fpgas revision 0 1-5 the external ddr memory are implemented in ha rdware. the ddr bridge contains three write combining / read buffers and one read buffer. all buffers within the ddr brid ge are implemented with seu tolerant latches and are not subject to the single event upsets (seus) that sram exhibits. smartfusion2 devices implement three ddr bridges in the mss, fddr, and mddr subsystems . ahb bus matrix (abm) the ahb bus matrix (abm) is a non-blocking, ah b-lite multi-layer switch, supporting 10 master interfaces and 7 slave interfaces. the switch deco des access attempts by ma sters to various slaves, according to the memory map and security configur ations. when multiple masters are attempting to access a particular slave simultaneously, an arbite r associated with that slave decides which master gains access, according to a configurable set of arbi tration rules. these rules can be configured by the user to provide different usage patterns to each slav e. for example, a number of consecutive access opportunities to the slave can be allocated to one part icular master, to increase the likelihood of same type accesses (all reads or all writes ), which makes more efficient usage of the bandwidth to the slave. system registers the mss system registers are implemented as an ah b slave on the ahb bus matrix. this means the cortex-m3 processor or a soft master in the fpga fabric may access the registers and therefore control the mss. the system registers can be initialized by user-defined flash configuration bits on power-up. each register also has a flash bit to enable write prot ecting the contents of the registers. this allows the mss system configuration to be reliably fixed fo r a given application. fabric interface controller (fic) the fic block provides two separate interfaces between the mss and the fpga fabric: the mss master (mm) and fabric master (fm). each of these interf aces can be configured to operate as ahb-lite or apb3. depending on device density, there are up to two fic blocks present in the mss (fic_0 and fic_1). embedded sram (esram) the mss contains two blocks of 32 kb esram, giving a total of 64 kb. having the esram arranged as two separate blocks allows the user to take ad vantage of the harvard arch itecture of the cortex-m3 processor. for example, code could be located in one esram, while data, such as the stack, could be located in the other. the esram is designed for single error correct double error detect (secded) protection. when secded is disabled, the sram usually used to st ore secded data may be reused as an extra 16 kb of esram. embedded nvm (envm) the mss contains up to 512 kb of envm (64 bits wide). accesses to the envm from the cortex-m3 processor are cacheable.
smartfusion2 device family overview 1-6 revision 0 dma engines two dma engines are present in the mss: high performance dma and peripheral dma. high performance dma (hpdma) the high-performance dma (hpdma) engine provides efficient memory to memory data transfers between an external ddr memory and internal esram. this engine has two separate ahb-lite interfaces?one to the mddr bridge and the other to the ahb bus matrix. all transfers by the hpdma are full word transfers. peripheral dma (pdma) the peripheral dma engine (pdma) is tuned for offloading byte-intensive operations, involving mss peripherals, to and from the internal esrams. data tr ansfers can also be targeted to user logic/ram in the fpga fabric. apb configuration bus on every smartfusion2 device memory, an apb configurat ion bus is present to allow the user to initialize the serdes asic blocks, the fabric ddr memory controller, and user instantiated peripherals in the fpga fabric. peripherals a large number of communications and general purpose peripherals are implemented in the mss. usb controller the mss contains a high speed usb 2.0 on-the-g o (otg) controller with the following features: ? operates either as the function controller of a high-speed / full-speed usb peripheral or as the host/peripheral in point-to-point or multi-point communications with other usb functions. ? complies with the usb 2.0 standard fo r high-speed functions and with the on-the-go supplement to the usb 2.0 specification. ? supports otg communications with one or more high-speed, full-speed, or low-speed devices. tse ethernet mac the triple speed ethernet (tse) mac supports ieee 802.3 10/100/1000mbps ethe rnet operation. the following phy interfaces are directly supported by the mac: ?rmii ?gmii ?mii ?tbi the ethernet mac hardware impl ements the following functions: ? 4 kb internal transmit fifo and 8 kb internal receive fifo ? ieee 802.3x full-duplex flow control ? dma of ethernet frames between internal fi fos and system memory (such as esram or ddr) ? cut-through operation ? secded protection on internal fifos sgmii phy interface sgmii mode is implemented by means of configur ing the mac for 10-bit interface (tbi) operation, allocating one of the high-speed serial channels to sg mii and by implementing custom logic in the fabric. 10 gbps ethernet support for 10 gbps ethernet is achieved by progra mming the serdes interface to xaui mode. in this mode, a soft 10g emac with xgmii interface can be directly conne cted to the serdes. interface.
smartfusion2 system-on-chip fpgas revision 0 1-7 communication block (comm_blk) the comm block provides a uart-like communic ations channel between the mss and the system controller. system services are initiated throu gh the comm block. system services such as enter flash*freeze mode are initiated though this block. spi the serial peripheral interface controller is compliant with the motorola spi, texas instruments synchronous serial, and national semiconductor micr owire? formats. in addition, the spi supports interfacing to large spi flash and eeprom devices by way of the slave protocol engine. the spi controller supports both master and slave modes of operation. the spi controller embeds two 432 (depth width) fifos for receive and transmit. these fifos are accessible through rx data and tx data registers. writ ing to the tx data register causes the data to be written to the transmit fifo. this is emptied by transmit logic. similarly, reading from the rx data register causes data to be read from the receive fifo. multi-mode uart (mmuart) smartfusion2 devices contain two identical multi-mode universal asynchronous/synchronous receiver/transmitter (mmuart) peripherals that pr ovide software compatibility with the popular 16550 device. they perform serial-to-parallel conversion on data originating from modems or other serial devices, and perform parallel-to-se rial conversion on data from the cortex-m3 processor to these devices. the following are the main features supported: ? fractional baud rate capability ? asynchronous and synchronous operation ? full programmable serial interface characteristics ? data width is programmable to 5, 6, 7, or 8 bits ? even, odd, or no-parity bit generation/detection ? 1,1?, and 2 stop bit generation ? 9-bit address flag capability used for multidrop addressing topologies i 2 c smartfusion2 devices contain tw o identical master/slave i 2 c peripherals that perform serial to-parallel conversion on data originating from serial devices, and perform parallel-to-serial conversion on data from the arm cortex-m3 processor, or any other bus ma ster, to these devices. the following are the main features supported: ?i 2 c v2.1 ? 100 kbps ? 400 kbps ? dual-slave addressing ?smbus v2.0 ?pmbus v1.1
smartfusion2 device family overview 1-8 revision 0 clock sources: on-chip oscillators, plls, and cccs smartfusion2 devices have two on-chip rc oscillators?a 1 mhz rc oscillator and a 50 mhz rc oscillator?and up to two main crystal oscillators ( 32 khz?20 mhz). these are available to the user for generating clocks to the on-chip resources and the lo gic built on the fpga fabric array. the second crystal oscillator available on the smartfusion2 devic es is dedicated for rtc clocking. these oscillators (except the rtc crystal oscillator) can be used in conjunction with th e integrated user phase-locked loops (plls) and fab_cccs to generate clocks of varying frequency and phase. in addition to being available to the user, these oscillators are also used by the system controller, power-on reset circuitry, mss during flash*freeze mode, and the rtc. smartfusion2 devices have up to eight fabric ccc (fab_ccc) blocks and a dedicated pll associated with each ccc to provide flexible clocking to the fp ga fabric portion of the device. the user has the freedom to use any of the eight p lls and cccs to generate the fa bric clocks and the internal mss clock from the base fabric clock (clk_base). there is also a dedicated ccc block for the mss (mss_ccc) and an associated pll (mpll) fo r mss clocking and de-skewing the clk_base clock. the fabric alignment clock controller (facc), part of the mss ccc, is responsible for generating various aligned clocks required by the mss for co rrect operation of the mss blo cks and synchornous communication with the user logic in the fpga fabric. high speed seri al interfaces serdes interface smartfusion2 has up to four 5 gbps serdes transceivers, each supporting the following: ? 4 serdes/pcs lanes ? the native serdes interface facilitates implementa tion of serial rapidio (s rio) in fabric or an sgmii interface for the ethernet mac in mss pci express (pcie) pcie is a high speed, packet-based, point-to-poin t, low pin count, serial interconnect bus. the smartfusion2 family has two hard high-speed serial interface blocks. each serdes block contains a pcie (pci express) system block. the pcie system is connected to the serdes block and following are the main features supported: ? supports x1, x2 and x4 lane configuration ? endpoint configuration only ? pci express base specification revision 2.0 ? 2.5 and 5.0 gbps compliant ? embedded receive (2 kb), transmit (1 kb) and retry (1 kb) buffer dual-port ram implementation ? 256 bytes maximum payload size ? 64-bit axi or 32-bit/64-bit ahbl master an d slave interface to the application layer ? 32-bit apb interface to acce ss configuration and status registers of pcie system ? up to 3 x 64 bit base address registers ? 1 virtual channel (vc) ? intel?s pipe interface (8-bit/16-bit) to interface between the phy mac and phy (serdes) ? fully compliant phy pcs sub-layer (125/250 mhz) xaui/xgxs extension the xaui/xgxs extension allows the user to implem ent a 10 gbps (xgmii) ethernet phy interface by connecting the ethernet ma c fabric interface through an appropria te soft ip block in the fabric.
smartfusion2 system-on-chip fpgas revision 0 1-9 high speed memory interfaces: ddrx memory controllers there are up to two ddr subsystems, mddr (mss ddr) and fddr (fabric ddr) present in smartfusion2 devices. each sub system consists of a ddr controlle r, phy and a wrapper. the mddr has an interface from the mss and fabric and fddr provides an interface from the fabric. the following are the main featur es supported by fddr and mddr: ? support for lpddr, ddr2, and ddr3 memories ? support for sdram memories ? simplified ddr command interface to standard amba axi/ahb interface ? up to 667 mbps (333 mhz double data rate) performance ? supports 1, 2, or 4 ranks of memory ? supports different dram bus width modes: x16, x18, x32, and x36 ? supports dram burst length of 2, 4, or 8 in fu ll bus-width mode; supports dram burst length of 2, 4, 8, or 16 in half bus-width mode ? supports memory densities up to 4 gb ? supports a maximum of 8 memory banks ? secded enable/disable feature ? embedded physical interface (phy) ? read and write buffers in fully associative cams , configurable in powers of 2, up to 64 reads plus 64 writes ? support for dynamically changing clock frequency while in self-refresh. ? supports command reordering to optimize memory efficiency ? supports data reordering, returning critical word first for each command mddr subsystem the mddr subsystem has two interfaces to the ddr. one is an axi 64-bit bus from the ddr bridge within the mss. the other is a mult iplexed interface from the fpga fabric, which can be configured as either a single axi 64-bit bus or two 32-bit ahb-lite buses. there is also a 16-bit apb configuration bus, which is used to initialize the majority of the in ternal registers within the mddr subsystem after reset. this apb configuration bus can be mastered by the m ss directly or by a master in the fpga fabric. fddr subsystem the fddr subsystem has one interface to the ddr. this is a multiplexed interf ace from the fpga fabric, which can be configured as ei ther a single axi 64-bit bus or two 32-bit ahb-lite buses. there is also a 16-bit apb configuration bus, which is used to initialize the ma jority of the intern al registers within the fddr subsystem after reset. th is apb configuration bus can be ma stered by the mss directly or by a master in the fpga fabric.

revision 0 2-1 advance information (s ubject to change) 2 ? smartfusion2 dc and switching characteristics general specifications operating conditions table 2-1 ? recommended operating conditions symbol parameter conditions min. typ. max. units notes t j junction temperature commercial 0 25 85 c junction temperature industrial ?40 25 100 c vdd dc core supply voltage 1.14 1.2 1.26 v vpp power supply for charge pumps (for normal opeartion and programming) 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v pllx_vdda analog power supply for pll0 to pll5 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v pll_pcie_x_vdda auxiliary power supply voltage by core to macro 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v pll_mddr_vdda analog power supply for pll mddr 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v pll_fddr_vdda analog power supply for pll fddr 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v pciexvdd pcie/pcs power supply 1.14 1.2 1.26 v pciexvddio[l/r] tx/rx analog i/ o voltage supply 1.14 1.2 1.26 v pciexvddpll[l/r] anlog power supply for serdes pll of pcie 2.375 2.5 2.625 v vddix 1.2 v dc supply voltage 1.14 1.2 1.26 v 1.5 v dc supply voltage 1.425 1.5 1.575 v 1.8 v dc supply voltage 1.71 1.8 1.89 v 2.5 v dc supply voltage 2.375 2.5 2.625 v 3.3 v dc supply voltage 3.15 3.3 3.45 v lvds differential i/o 2.375 2.5 3.45 v b-lvds, m-lvds, mini-lvds, rsds differential i/o 2.375 2.5 2.625 v lvpecl differential i/o 3.15 3.3 3.45 v vrefx reference voltage supply for fddr (bank 0) and mddr (bank 5) 0.49 * vddi0 0.5 * vddi0 0.51 * vddi0 v vccenvm embedded nonvolatile memory supply 2.5 v range 2.375 2.5 2.625 v 3.3 v range 3.15 3.3 3.45 v
smartfusion2 dc and switching characteristics 2-2 revision 0 advance information (s ubject to change) power supply sequencing and po wer-on reset (c ommercial and industrial) sophisticated power-up management circuitry is de signed into every smartfusion2 soc fpga. these circuits ensure easy transition from powered-off state to powered-up state of the device. the smartfusion2 system controller is responsible for systematic power-on reset whenever the device is powered on or reset. all the i/os ar e held in a high-impedance state by the system controller until all power supplies are at thei r required levels and the system contro ller has completed the reset sequence. the power-on reset circuitry in smartfusion2 devices requires the vdd supply to ramp at a predefined rate. four ramp rate options are available duri ng design generation: 50 s, 100 s, 1 ms, and 100 ms. table 2-2 ? fpga and embedded flash programming, storage and operating limits product grade storage temperature programming temperature element grade programming cycles retention commercial min. t j = 0c max. t j = 85c min. t j = 0c max. t j = 85c fpga 500 20 years min. t j = 0c max. t j = 85c embedded flash < 1,000 20 years < 10,000 10 years industrial min. t j = ?40c max. t j = 100c min. t j = 0c max. t j = 85c fpga 500 20 years min. t j = ?40c max. t j = 100c embedded flash < 1,000 20 years < 10,000 10 years
smartfusion2 system-on-chip fpgas revision 0 2-3 advance information (s ubject to change) thermal characteristics introduction the temperature variable in the soc products group designer software refers to the junction temperature, not the ambi ent, case, or board temp eratures. this is an im portant distinction because dynamic and static power consumption will cause the ch ip's junction temperature to be higher than the ambient, case, or board temperatures. eq 1 through eq 3 give the relationship between thermal resistance, temperature gradient, and power. eq 1 eq 2 eq 3 where ja = junction-to-air thermal resistance jb = junction-to-board thermal resistance jc = junction-to-case thermal resistance t j = junction temperature t a = ambient temperature t b = board temperature (measured 1.0 mm away from the package edge) t c = case temperature p = total power dissipated by the device table 2-3 ? package thermal resistance product ja jc jb units still air 1.0 m/s 2.5 m/s m2s050t-fg896 14.7 12.5 10.9 7.2 4.9 c/w ja t j a ? p ------------------ = jb t j t b ? p ------------------ - = jc t j t c ? p ------------------- =
smartfusion2 dc and switching characteristics 2-4 revision 0 advance information (s ubject to change) theta-ja junction-to-ambient thermal resistance ( ja ) is determined under standa rd conditions specified by jedec (jesd-51), but it has little relevance in actual performance of the product. it should be used with caution but is useful for comparing the th ermal performance of one package to another. the maximum power dissipation allowed is calculated using eq 4 . eq 4 the absolute maximum juncti on temperature is 100c. eq 5 shows a sample calculation of the absolute maximum power dissipation allowed for the m2s050 t-fg896 package at commercial temperature and in still air, where eq 5 the power consumption of a device can be calcul ated using the microsemi soc products group power calculator. the device's power consumption must be lower than the calculated maximum power dissipation by the package. if the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be attached on to p of the case, or the airflow inside the system must be increased. theta-jb junction-to-board thermal resistance ( jb ) measures the ability of the pa ckage to dissipate heat from the surface of the chip to the pcb. as defined by t he jedec (jesd-51) standard, the thermal resistance from junction to board uses an isothermal ring cold plate zone concept. the ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. the cold plate is mounted on a jedec standard board with a minimum distanc e of 5.0 mm away from the package edge. theta-jc junction-to-case thermal resistance ( jc ) measures the ability of a devic e to dissipate heat from the surface of the chip to the top or bottom surface of the pa ckage. it is applicable for packages used with external heat sinks. constant temperature is applie d to the surface in consideration and acts as a boundary condition. this only applies to situations wher e all or nearly all of the heat is dissipated through the surface in consideration. ja = 14.7c/w (taken from table 2-3 on page 2-3 ). t a = 85c maximum power allowed t j(max) t a(max) ? ja --------------------------------------------- = maximum power allowed 100c 85c ? 14.7c/w ------------------------------------ 1.088 w ==
smartfusion2 system-on-chip fpgas revision 0 2-5 advance information (s ubject to change) calculating power dissipation quiescent supply current i/o power table 2-4 ? quiescent supply current characteristics parameter modes m2s050t units vdd = 1.2 v idc1 active mode 7.5 ma idc2 standby mode 7.5 ma idc3 flash*freeze mode 0.387 ma table 2-5 ? summary of i/o input bu ffer power (per pin) using default softw are setting with technology selected msio i/o bank msiod i/o bank ddr i/o bank notes static power dynamic power static power dynamic power static power dynamic power pdc8 (mw) pac9 (w/mhz) pdc8 (mw) pac9 (w/mhz) pdc8 (mw) pac9 (w/mhz) single ended i/o standards 1.2 v lvcmos (jesd8-11) 0.00 11.72 0.00 11.72 0.00 11.72 1.5 v lvcmos (jesd8-11) 0.00 8.32 0.00 8.32 0.00 8.32 1.8 v lvcmos 0.00 10.69 0.00 10.69 0.00 10.69 2.5 v lvcmos 0.00 4.14 0.00 4.14 0.00 4.14 3.3 v lvttl / 3.3 v lvcmos 0.00 5.47 ? ? ? ? 3.3 v pci/pcix 0.00 1.82 ? ? ? ? memory interface and voltage reference standard hstl 1.5 v 2.21 5.57 2.21 5.57 2.21 5.57 hstl 1.5 v ? true differential 1.25 47.38 1.25 47.38 1.25 47.38 sstl2/ddr 10.02 42.68 10.02 42.68 10.02 42.68 sstl2/ddr ? true differential 4.39 12.35 4.39 12.35 4.39 12.35 sstl18/ddr2 3.88 3.81 3.88 3.81 3.88 3.81 sstl18/ddr2 ? true differential 1.97 56.80 1.97 56.80 1.97 56.80 sstl15/ddr3 ? ? ? ? 2.20 18.00 sstl15/ddr3 ? true differential ? ? ? ? 1.23 46.81 lpddr ? ? ? ? 3.88 4.46 lpddr ? true differential ? ? ? ? 1.97 5.08 differential standards lvds 5.74 17.65 5.74 17.65 ? ? b-lvds 5.65 8.76 5.65 8.76 ? ? m-lvds 5.65 8.76 5.65 8.76 ? ? rsds 5.74 0.93 5.74 0.93 ? ? mini-lvds tbd tbd tbd tbd ? ? lvpecl tbd tbd ? ? ? ?
smartfusion2 dc and switching characteristics 2-6 revision 0 advance information (s ubject to change) table 2-6 ? summary of i/o output buffer power (per pin) default software setting with technology selected msio i/o bank msiod i/o bank ddr i/o bank notes static power dynamic power static power dynamic power static power dynamic power pdc9 (mw) pac9 (w/mhz) pdc9 (mw) pac9 (w/mhz) pdc9 (mw) pac9 (w/mhz) single ended i/o standards 1.2 v lvcmos (jesd8-11) 0.00 16.74 0.00 16.74 0.00 16.74 1.5 v lvcmos (jesd8-11) 0.00 26.31 0.00 26.31 0.00 26.31 1.8 v lvcmos 0.00 38.23 0.00 38.23 0.00 38.23 2.5 v lvcmos 0.00 75.35 0.00 75.35 0.00 75.35 3.3 v lvttl / 3.3 v lvcmos 0.00 137.04 ? ? ? ? 3.3 v pci/pcix 0.00 tbd ? ? ? ? memory interface and voltage reference standard hstl 1.5 v class i 6.45 60.17 6.45 60.17 6.45 60.17 hstl 1.5 v class i ? true differential 12.90 80.30 12.90 80.30 12.90 80.30 hstl 1.5 v class ii ? ? ? ? 12.56 104.21 hstl 1.5 v class ii ? true differential ? ? ? ? 25.08 87.09 sstl2 class i / ddr reduced drive 18.12 76.44 18.12 76.44 18.12 76.44 sstl2 class i / ddr reduced drive ? true differential 36.16 218.81 36.16 218.81 36.16 218.81 sstl2 class ii / ddr full drive 37. 20 317.68 37.20 317.68 37.20 317.68 sstl2 class ii / ddr full drive ? true differential 74.41 110.90 74.41 110.90 74.41 110.90 sstl18 class i / ddr2 reduced drive 9.06 15.09 9.06 15.09 9.06 15.09 sstl18 class i / ddr2 reduced drive ? true differential 18.09 56.33 18.09 56.33 18.09 56.33 sstl18 class ii / ddr2 full drive 18.63 170.66 18.63 170.66 18.63 170.66 sstl18 class ii / ddr2 full drive ? true differential 37.28 9.12 37.28 9.12 37.28 9.12 sstl15 class i / ddr3 reduced drive ? ? ? ? 11.28 62.13 sstl15 class i / ddr3 reduced drive ? true differential ? ? ? ? 22.52 131.80 sstl15 class ii / ddr3 full drive ? ? ? ? 12.15 47.65 sstl15 class ii / ddr3 full drive ? true differential ? ? ? ? 24.29 142.98 lpddr reduced drive ? ? ? ? 18.62 331.33 lpddr reduced drive ? true differential ? ? ? ? 37.28 9.12 lpddr full drive ? ? ? ? 9.06 46.40 lpddr full drive ? true differential ? ? ? ? 18.09 56.33 differential standards lvds 13.48 63.84 13.48 63.84 ? ? b-lvds 18.37 30.73 ? ? ? ? m-lvds 18.37 30.73 ? ? ? ? rsds 8.50 82.76 8.50 82.76 ? ? mini-lvds tbd tbd tbd tbd ? ?
smartfusion2 system-on-chip fpgas revision 0 2-7 advance information (s ubject to change) power consumption of vari ous internal resources table 2-7 ? different components contributing to dynamic power consumption in smartfusion2 devices param. definition power supply device units notes name domain m2s050t pac1 global clock contribution of a gb vdd 1.2 v 3.50 w/mhz pac2 global clock contribution of a rgb vdd 1.2 v 0.87 w/mhz pac3 global clock contribution of a sequential module. vdd 1.2 v 0.02 w/mhz pac4 clock contribution of a sequential module. vdd 1.2 v 0.01 w/mhz pac5 data contribution of a sequent ial module. vdd 1.2 v 0.06965 w/mhz pac6 average contribution of a combi natorial module. vdd 1.2 v 0.709 w/mhz pac7 average contribution of a combinatorial module with carry chain. vdd 1.2 v 0.821657 w/mhz pac8 average contribution of a routing net. vdd 1.2 v 0.87 w/mhz pac9 contribution of an i/o input pin (standard dependent) vddi table 2-5 on page 2-5 ta b l e 2 - 5 on page 2-5 ? pac10 contribution of an i/o output pin (standard dependent) vddi table 2-6 on page 2-6 ta b l e 2 - 6 on page 2-6 ? pac11 average contribution of a usram block during a read operation. vdd 1.2 v 2.39 w/mhz pac12 average contribution of a usram block during a write operation. vdd 1.2 v 7.01 w/mhz pac13 average contribution of a lsram block during a read operation. vdd 1.2 v 19.85 w/mhz pac14 average contribution of a lsram block during a write operation. vdd 1.2 v 24.85 w/mhz pac15 ccc contribution vdd 1.2 v 8.00 mw pac16 main crystal oscillator contribution vdd 1.2 v 55.51 w/mhz pac17 1 mhz rc oscillator contribution vdd 1.2 v 37.2 mw pac18 50 mhz rc oscillator contribution vdd 1.2 v 7.30 mw pac19 math block contribution vdd 1.2 v tbd mw pac20 mss dynamic power contribution with mddr/usb/ethernet off, clock frequency = 100 mhz vdd 1.2 v 91.986 mw 1 pac21 mss dynamic power contribution with usb/ethernet off, clock frequency = 100 mhz, mddr mode?mss bridge vdd 1.2 v 137.43 mw 1 notes: 1. for a different use of mss peripherals and resources, refer to smartpower. 2. dynamic power contribution of fddr does not include the ddrio power. use i/o power for calculation of i/o power. for a different use of the fddr, refer to smartpower. 3. for a different use of the serdes block, refer to smartpower.
smartfusion2 dc and switching characteristics 2-8 revision 0 advance information (s ubject to change) pac22 fddr dynamic power contribution with frequency = 100 mhz, ddr clock multiplier = 2 vdd 1.2 v 108.81 mw 2 pac23 serdes dynamic power contribution configured as pcie_gen1 with 1 lane at 125 mhz vdd 1.2 v 91.70 mw 3 table 2-8 ? different components contributi ng to the static power consumption in smartfusion devices param. definition power supply device units name domain mode m2s050t pdc1 core static power contribution in active operating mode vdd 1.2 v active 9.000 mw pdc2 core static power contribution in standby operating mode vdd 1.2 v standby 9.000 mw pdc3 core static power contribution in flash*freeze operating mode vdd 1.2 v flash*freeze 0.465 mw pdc4 lsram static power contribution in flash*freeze configured in "sleep" state vdd 1.2 v flash*freeze 1.250 uw pdc5 lsram static power contribution in flash*freeze configured in "suspended" state vdd 1.2 v flash*freeze 10.140 uw pdc6 usram static power contribution in flash*freeze configured in "sleep" state vdd 1.2 v flash*freeze 0.500 uw pdc7 usram static power contribution in flash*freeze configured in "suspend" state vdd 1.2 v flash*freeze 4.970 uw pdc8 i/o input static power contribution in active operating mode vddi vddi active see table 2-5 on page 2-5 uw pdc9 i/o output static power contribution in active operating mode vddi vddi active see table 2-6 on page 2-6 uw table 2-7 ? different components contributing to dynamic power consumption in smartfusion2 devices (continued) param. definition power supply device units notes name domain m2s050t notes: 1. for a different use of mss peripherals and resources, refer to smartpower. 2. dynamic power contribution of fddr does not include the ddrio power. use i/o power for calculation of i/o power. for a different use of the fddr, refer to smartpower. 3. for a different use of the serdes block, refer to smartpower.
smartfusion2 system-on-chip fpgas revision 0 2-9 advance information (s ubject to change) power methodology this section describes a simplified method to estima te power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in the libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls/cccs as well as the nu mber and the frequency of each output clock generated ? the number of combinatorial and sequential cells used in the design ? the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as the logic module?guidelines are provided in ta b l e 2 - 9 o n page 2-13 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-10 on page 2-13 . ? read rate and write rate to the memory?guidel ines are provided for typical applications in table 2-10 on page 2-13 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total active, standby and flash*freeze mode p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat active mode p stat = pdc1 + (n i nputs * pdc7) + (n outputs * pdc8) + (n plls * pdc9) n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. n plls is the number of plls available in the device. standby mode p stat = pdc2 flash*freeze mode p stat = pdc3 + pdc4 + pdc 6 when both lsram and usram are configured in sleep state p stat = pdc3 + pdc5 + pdc 7 when both lsram a nd usram are configured in suspend state total dynamic power consumption?p dyn active mode p dyn = p clock + p logic + p ios + p memory + p ccc + p math + p mss + p fddr + p serdes flash*freeze mode p dyn = pdc3 + p memory standby mode p dyn = pdc2
smartfusion2 dc and switching characteristics 2-10 revision 0 advance information (s ubject to change) global clock dynamic power contribution?p clock active mode p clock = (pac1 + n rows * pac2 + n s-cell * pac3) * f clk where: n rows is the number of global rows used in th e design?guidelines are provided in the "fabric global routing resources" chapter of the smartfusion2 fpga fabric architecture user's guide . f clk is the global clock signal frequency. n s-cell i s the number of registers used in the design. standby and flash*freeze mode p clock = 0 w logic module dynamic power contribution?p logic active mode p logic = p seq + p lut + p net standby and flash*freeze mode p logic = 0 w registers dynamic power contribution?p seq p seq = n s-cell * pac4 * f clk + n s-cell * pac5 * f clk * 1/2 where: n s-cell is the number of regi sters used in the design. 1 is the toggle rate of the lut ou tputs?guidelines are provided in table 2-9 on page 2-13 . f clk is the global clock signal frequency. luts dynamic power contribution?p lut p lut = (n lut * pac6 + n cc * pac7) * f clk * 1/2 where: n lut is the number of lut-4 used as co mbinatorial modules in the design. n cc is the number of lut-4 used with the carry chain in the design. 1 is the toggle rate of the lut ou tputs?guidelines are provided in table 2-9 on page 2-13 . f clk is the global clock signal frequency. routing net dynamic power contribution?p net p net = (n s-cell + n lut + n cc) * ( 1 / 2) * pac8 * f clk where: n s-cell is the number of registers used in the design. n lut is the number of lut-4 used as combinatorial modules in the design. n cc is the number of lut-4 used wit h the carry chain in the design. 1 is the toggle rate of the lut ou tputs?guidelines are provided in table 2-9 on page 2-13 . f clk is the global clock signal frequency. i/o dynamic contribution?p ios active mode p ios = p i nputs + p outputs standby and flash*freeze mode p ios = 0 w
smartfusion2 system-on-chip fpgas revision 0 2-11 advance information (s ubject to change) i/o input buffer dynamic contribution?p inputs pinputs = ninputs * ( 2 / 2) * 1 * pac9 * fclk where: n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-9 on page 2-13 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-10 on page 2-13 . f clk is the global clock signal frequency. i/o output buffer dynamic contribution?p outputs p outputs = n outputs * ( 2 / 2) * 1 * pac10 * f clk where: n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-9 on page 2-13 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-10 on page 2-13 . f clk is the global clock signal frequency. fpga fabric sram dynamic contribution?p memory active mode p memory = p usram + p lsram flash*freeze mode p memory = pdc4 + pdc6 for ram in "sleep" state p memory = pdc5 + pdc7 for ram in "suspend" state standby mode p memory = 0 w fpga fabric usram dynamic contribution ?p usram p usram = (n usram_blk * pac13 * 2 * f usram-rdclk ) + (n usram_blk * pac14 * 3 * f usram-wrtclk ) where: nu sram_blk is the number of uram blocks used in the design. f usram-rdclk is the usram memory read clock frequency. f usram-wrtclk is the usram memory write clock frequency. 2 is the ram enable rate for read operations?guidelines are provided in table 2-10 on page 2-13 . 3 the ram enable rate for write operations?guidelines are provided in table 2-10 on page 2-13 . fpga fabric large sram dynamic contribution?p lsram p lsram = (n lsram_blk * pac13 * 2 * f lsram-rdclk ) + (n lsram_blk * pac14 * 3 * f lsram-wrtclk ) where: n lsram_blk is the number of large sr am blocks used in the design. f lsram-rdclk is the large sram memory read clock frequency. f lsram-wrtclk is the large sram memory write clock frequency. 2 is the ram enable rate for read operations?guidelines are provided in table 2-10 on page 2-13 . 3 the ram enable rate for write operations?guidelines are provided in table 2-10 on page 2-13 .
smartfusion2 dc and switching characteristics 2-12 revision 0 advance information (s ubject to change) pll/ccc dynamic contribution?p pll active mode p pll = pac15 flash*freeze/standby mode p pll = 0 w external main crystal oscillator dynamic contribution?p xtl-osc active mode p xtl-osc = pac16 * f clk where: f clk is the output frequency of the oscillator. flash*freeze/standby mode p xtl-osc = 0 w on-chip 25/50mhz rc oscillator dynamic contribution? p 50rc-osc active mode/s tandby mode p 50rc-osc = 0 w flash*freeze when used by mss: p 50rc-osc = pac18 when not used by mss: p 50rc-osc = 0 w math block dynamic power contribution?p math active mode p math = pac19 * n math_blk * f mathclk n math_blk is the number of math blocks used in the design. f mathclk is the math block clock frequency. flash*freeze/standby mode p math = 0 w microcontroller subsystem dynamic power contribution?p mss active mode with mddr off: p mss = pac20 with mddr on: p mss = pac21 flash*freeze/standby mode p mss = 0 w
smartfusion2 system-on-chip fpgas revision 0 2-13 advance information (s ubject to change) fddr dynamic power contribution?p fddr active mode pfddr = pac22 fddr dynamic power contributions do not include the power contributi ons of the ddr i/o. this should be accounted for in the i/o power calculations. flash*freeze/standby mode p fddr = 0 w serdes contribution?p serdes active mode p serdes = pac23 flash*freeze/standby mode p serdes = 0 w guidelines toggle rate definition a toggle rate defines the frequency of a net or logic elem ent relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this m eans that the net switches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% , as all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8. enable rate definition output enable rate is the average percentage of ti me during which tristate outputs are enabled. when non-tristate output buffers are us ed, the enable rate should be 100%. table 2-9 ? toggle rate guidelines recommended for power calculation component defini tion guideline 1 toggle rate of logic module outputs 10% 2 ? i/o buffer toggle rate 10% table 2-10 ? enable rate guidelines recommended for power calculation component defini tion guideline 1 i/o output buffer enable rate toggle rate of the logic driving the output buffer 2 ? fpga fabric sram enable rate for read operations 12.50% 3 fpga fabric sram enable rate for write operations 12.50% 4 envm enable rate for read operations < 5%
smartfusion2 dc and switching characteristics 2-14 revision 0 advance information (s ubject to change) average fabric temperature and voltage derating factors table 2-11 ? average temperature and voltage derati ng factors for fabric timing delays (normalized to t j = 100c, worst-case vdd = 1.14 v) array voltage vcc (v) junction temperature (c) ?40c 0c 25c 70c 85c 100c 1.14 tbd tbd tbd tbd tbd tbd 1.2 tbd tbd tbd tbd tbd tbd 1.26 tbd tbd tbd tbd tbd tbd
smartfusion2 system-on-chip fpgas revision 0 2-15 advance information (s ubject to change) timing model figure 2-1 ? timing model dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (non-registered) lvds ddr3 lvds buffer buffer buffer sstl2 class i y combinational cell y combinational cell y combinational cell i/o module (non-registered) i/o module (non-registered) i/o module (registered) lvcmos 2.5 v output drive strength = 4x msio i/o bank i/o module (non-registered) lvcmos 1.5 v output drive strength = 12x ddrio i/o bank lvcmos 2.5 v output drive strength = 7x msio i/o bank input clock input clock input clock lvcmos 2.5 v lvcmos 2.5 v lvcmos 2.5 v a b e h j m p k i f g c d l m c c n o l buffer
smartfusion2 dc and switching characteristics 2-16 revision 0 advance information (s ubject to change) table 2-12 ? timing model parameters index parameter description value units notes a tpy propagation delay of ddr3 receiver tbd ns table 2-51 on page 2-51 b ticlkq clock-to-q of the input data register tbd ns table 2-73 on page 2-65 tisud setup time of the input data register tbd ns table 2-73 on page 2-65 c trckh input high delay for global clock tbd ns table 2-79 on page 2-76 trckl input low delay for global clock tbd ns table 2-79 on page 2-76 d tpy input propagation delay of lvds receiver tbd ns table 2-57 on page 2-55 e tdp propagation delay of a three input and gate 0.22 ns table 2-77 on page 2-73 f tdp propagation delay of a or gate 0.172 ns table 2-77 on page 2-73 g tdp propagation delay of a lvds transmitter tbd ns table 2-58 on page 2-55 h tdp propagation delay of a three input xor gate 0.24 ns table 2-77 on page 2-73 i tdp propagation delay of lvcmos 2.5 v transmitter, drive strength of 8x on the msio bank 2.481 ns table 2-25 on page 2-25 j tdp propagation delay of a two input mux gate 0.172 ns table 2-77 on page 2-73 k tdp propagation delay of lvcmos 2.5 v transmitter, drive strength of 4x on the msio bank 2.382 ns table 2-25 on page 2-25 l tclkq clock-to-q of the data register 0.114 ns table 2-78 on page 2-75 tsud setup time of the data register 0.267 ns table 2-78 on page 2-75 m tdp propagation delay of a two input and gate 0.172 ns table 2-77 on page 2-73 n toclkq clock-to-q of the output data register tbd ns table 2-73 on page 2-65 tosud setup time of the output data register tbd ns table 2-73 on page 2-65 o tdp propagation delay of sstl2, class i transmitter on the msio bank tbd ns table 2-46 on page 2-44 p tdp propagation delay of lvcmos 1.5 v transmitter, drive strength of 15x on the ddrio bank tbd ns table 2-33 on page 2-31
smartfusion2 system-on-chip fpgas revision 0 2-17 advance information (s ubject to change) user i/o characteristics there are three types of i/os supported in the smartfusion2 fpga family : msio, msiod, and ddrio i/o banks. the i/o standards supported by the different i/o banks is described in th e "i/os" section of the smartfusion2 fpga fabric architecture user?s guide . input buffer and ac loading t pys (r) pad y vtrip gnd t pys (f) t py (r) t py (f) vtrip 50% 50% vih vdd vil pad y t py t pys t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
smartfusion2 dc and switching characteristics 2-18 revision 0 advance information (s ubject to change) output buffer a nd ac loading t dp (r) vol t dp (f) vtrip vtrip voh d 50% 50% vdd 0 v out pad t dp cload d t dp t dp = max(t dp (r), t dp (f)) pad cload rtt vtt/vddi d t dp = max(t dp (r), t dp (f)) single-ended i/o test setup hstl/pci test setup t dp pad cload rtt d t dp = max(t dp (r), t dp (f)) voltage-referenced, singled-ended i/o test setup differential i/o test setup rs t dp t py pad_p pad_p in d t dp = max(t dp (r), t dp (f)) t py = max(t py (r), t py (f)) t pys = max(t pys (r), t pys (f)) z 0 = 50 ohms z 0 = 50 ohms pad_n pad_n d
smartfusion2 system-on-chip fpgas revision 0 2-19 advance information (s ubject to change) tristate buffer and ac loading the tristate path for enable path loadings is describ ed in the respective specifications. the methodology of characterization is illustrated by the enable path test point below. t hz t zh t lz 90% vddi 90% vddi 10% vddi 50% pad data (d) enable (e) 50% 10% vddi t zl 50% pad e d out t zl , t zh , t hz , t lz r ent to gnd for t zh , t hz 50%
smartfusion2 dc and switching characteristics 2-20 revision 0 advance information (s ubject to change) detailed i/o characteristics table 2-13 ? input capacitance symbol definition conditions minimum maximum units c in input capacitance vin = 0, f = 1.0 mhz ? 10 pf table 2-14 ? i/o weak pull-up/pu ll-down resistances for ddrio i/o bank minimum and maximum weak pull-up/pull -down resistance values at voh/vol level vddi domain ddrio i/o bank notes r(weak pull-up) at voh ( ) r(weak pull-down) at vol ( ) min. max. min. max. 3.3 v n/a n/a n/a n/a ? 2.5 v 10.6 k 17.3 k 10.5 k 18.1 k 1, 2 1.8 v 1.11 k 19.3 k 11.2 k 20.9 k 1, 2 1.5 v 10 k 13.4 k 9.99 k 13.4 k 1, 2 1.2 v 10.3 k 14.5 k 10.3 k 14.7 k 1, 2 notes: 1. r(weak pull-down) = (volspec)/i(weak pull-down max) 2. r(weak pull-up) = (vddimax - vohspec)/i(weak pull-up min) table 2-15 ? i/o weak pull-up/pull-down resistances for msio i/o bank minimum and maximum weak pull-up/pull -down resistance values at voh/vol level vddi domain msio io bank notes r(weak pull-up) at voh ( ) r(weak pull-down) at vol ( ) min. max. min. max. 3.3 v 9.9 k 14.7 k 10.1 k 15.3 k ? 2.5 v 10.1 k 15.1 k 10.1 k 15.7 k 1, 2 1.8 v 10.4 k 16.2 k 10.4 k 17.3 k 1, 2 1.5 v 10.7 k 17.3 k 10.8 k 18.9 k 1, 2 1.2 v 11.3 k 19.7 k 11.5 k 22.7 k 1, 2 notes: 1. r(weak pull-down) = (volspec)/i(weak pull-down max) 2. r(weak pull-up) = (vddimax - vohspec)/i(weak pull-up min)
smartfusion2 system-on-chip fpgas revision 0 2-21 advance information (s ubject to change) table 2-16 ? i/o weak pull-up/pull-down resistances for msiod i/o bank minimum and maximum weak pull-up/pull -down resistance values at voh/vol level vddi domain r(weak pull-up) at voh ( ) r(weak pull-down) at vol ( ) notes min. max. min. max. 3.3 v n/a n/a n/a n/a ? 2.5 v 9.6 k 14.1 k 9.5 k 13.9 k 1, 2 1.8 v 9.7 k 14.7 k 9.7 k 14.5 k 1, 2 1.5 v 9.9 k 15.3 k 9.8 k 15 k 1, 2 1.2 v 10.3 k 16.7 k 10 k 16.2 k 1, 2 notes: 1. r(weak pull-down) = (volspec)/i(weak pull-down max) 2. r(weak pull-up) = (vddimax - vohspec)/i(weak pull-up min) table 2-17 ? schmitt trigger input hysteresis hysteresis voltage value for sc hmitt trigger mo de input buffers input buffer configuration hysteresis value (typical, unless otherwise noted) 3.3 v lvttl / lvcmos / pci / pci-x 0.05 vddi (worst-case) 2.5 v lvcmos 0.05 vddi (worst-case) 1.8 v lvcmos 0.1 vddi (worst-case) 1.5 v lvcmos 60 mv 1.2 v lvcmos 20 mv
smartfusion2 dc and switching characteristics 2-22 revision 0 advance information (s ubject to change) single-ended i/o standards low voltage complementary meta l oxide semiconductor (lvcmos) lvcmos is a widely used switching standard implemen ted in cmos transistors. this standard is defined by jedec (jesd 8-5). the lvcmos standards supported in smartfusion2 soc fpgas are lvcmos12, lvcmos15, lvcmos18, and lvcmos25 and lvcmos33. 3.3 v lvcmos/lvttl lvcmos 3.3 v or low-voltage transistor-transistor logic (lvttl) is a general standard for 3.3 v applications. minimum and maximum dc/ac input a nd output levels specification table 2-18 ? lvttl/lvcmos 3.3 v dc voltage specification symbol parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 3.15 3.3 3.45 v lvttl/lvcmos 3.3 v dc input voltage specification vih (dc) dc input logic high 2.0 ? 3.45 v vil (dc) dc input logic low ?0.3 ? 0.8 v iih (dc) input current high ? ? 10 ma iil (dc) input current low ? ? 10 ma lvcmos 3.3 v dc output voltage specification voh dc output logic high vddi ? 0.4 ? ? v 1 vol dc output logic low ? ? 0.4 v 1 lvttl 3.3 v dc output voltage specification voh dc output logic high 0.4 ? ? v vol dc output logic low ? ? 2.4 v lvttl/lvcmos 3.3 v ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ? ? 600 mbps lvttl/lvcmos 3.3 v ac test parameters specifications vtrip measuring/trip point for data path ? 1.4 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ? 5 ? pf cload capacitive loading for data path (tdp) ? 5 ? pf notes: 1. the voh/vol test points selected ensure compliance with lvcmos 3.3 v jesd8-b requirements.
smartfusion2 system-on-chip fpgas revision 0 2-23 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 3.0 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-19 ? lvttl/lvcmos 3.3 v transmitter drive strength specifications output drive selection voh (v) vol (v) ioh (at voh) ma iol (at vol) ma notes msio i/o bank 1 vddi ? 0.4 0.4 2 2 2 vddi ? 0.4 0.4 4 4 3 vddi ? 0.4 0.4 8 8 4 vddi ? 0.4 0.4 12 12 6 vddi ? 0.4 0.4 16 16 8 vddi ? 0.4 0.4 20 20 table 2-20 ? lvcmos 3.3 v receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. lvcmos 3.3 v (for msio i/o bank) none 2.46 2.893 2.408 2.833 ns table 2-21 ? lvcmos 3.3 v transmi tter characteristics output drive selection slew control tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvcmos 3.3 v (for msio i/o bank) 1 ? 3.274 3.853 3.459 4.069 3.269 3 .845 3.608 4.244 3.419 4.022 ns 2 ? 2.418 2.845 2.914 3.427 4.35 5.116 3.064 3.604 4.5 5.293 ns 3 ? 2.221 2.614 4.195 4.935 4.695 5.523 4.345 5.112 4.845 5.7 ns 4 ? 2.128 2.505 5.135 6.041 5.105 6 .005 5.285 6.218 5.255 6.182 ns 6 ? 2.147 2.526 5.776 6.795 5.451 6 .412 5.926 6.972 5.601 6.589 ns 8 ? 2.228 2.622 5.958 7.009 5.691 6 .695 6.108 7.186 5.841 6.872 ns
smartfusion2 dc and switching characteristics 2-24 revision 0 advance information (s ubject to change) lvcmos 2.5 v lvcmos 2.5 v is a general standard for 2.5 v applic ations and is supported in smartfusion2 fpgas in compliance to the jedec specification jesd8-5a. minimum and maximum dc input and output levels specification table 2-22 ? lvcmos 2.5 v dc voltage specification symbol parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 2.625 v lvcmos 2.5 v dc input voltage specification vih (dc) dc input logic high for (msiod and ddrio i/o bank) 1.7 ? 2.625 v vih (dc) dc input logic high (for msio i/o bank) 1.7 ? 3.45 v vil (dc) dc input logic low ?0.3 ? 0.7 v iih (dc) input current high ? ? ? ma iil (dc) input current low ? ? ? ma lvcmos 2.5 v dc output voltage specification voh dc output logic high vddi ? 0.4 ? ? v 1 vol dc output logic low ? ? 0.4 v 1 lvcmos 2.5 v ac specifications fmax maximum data rate (for ddrio i/o bank) ac loading: 5 pf load, maximum drive/slew ? ? 250 mbps fmax maximum data rate (for msio i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ? ? 410 mbps fmax maximum data rate (for msiod i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ? ? 420 mbps supported output driver calibrated impedance (for ddrio i/o bank) 75, 60, 50, 33, 25, 20 ohms lvcmos 2.5 v ac test parameters specifications vtrip measuring/trip point for data path 1.2 v rent resistance for enable path (tzh, tzl, thz, tlz) 2k ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) 5 pf cload capacitive loading for data path (tdp) 5 pf notes: 1. the voh/vol test points selected ensure compliance with lvcmos 2.5 v jedec8-5a requirements .
smartfusion2 system-on-chip fpgas revision 0 2-25 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 3.0 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-23 ? lvcmos 2.5 v transmitter dr ive strength specifications output drive selection voh (v) vol (v) ioh (at voh) ma iol (at vol) ma notes msio i/o bank msiod i/o bank ddrio i/o bank min. max. 1 2 2 vddi ? 0.4 0.4 2 2 2 3 4 vddi ? 0.4 0.4 4 4 3 4 5 vddi ? 0.4 0.4 6 6 4 6 7 vddi ? 0.4 0.4 8 8 5 8 10 vddi ? 0.4 0.4 12 12 7 n/a 14 vddi ? 0.4 0.4 16 16 table 2-24 ? lvcmos 2.5 v receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. lvcmos 2.5 v (for ddrio i/o bank) n/a tbd tbd tbd tbd ns lvcmos 2.5 v (for msio i/o bank) n/a 2.594 3.052 2.561 3.013 ns lvcmos 2.5 v (for msiod i/o bank) n/a tbd tbd tbd tbd ns table 2-25 ? lvcmos 2.5 v transmi tter characteristics output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenzh units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvcmos 2.5 v (for ddrio i/o bank with fied codes) 2 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 4 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 5 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-26 revision 0 advance information (s ubject to change) 7 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 10 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 14 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns lvcmos 2.5 v (for msio i/o bank) 1 none 3.534 4.158 3.816 4.489 3.742 4.402 3.888 4.574 3.814 4.487 ns 2 none 2.651 3.118 3.898 4.586 4.625 5.441 3.971 4.672 4.698 5.527 ns 3 none 2.463 2.898 4.794 5.639 4.994 5.875 4.867 5.725 5.067 5.961 ns 4 none 2.382 2.802 5.724 6.734 5.417 6.373 5.797 6.82 5.49 6.459 ns 5 none 2.405 2.829 5.883 6.921 5.593 6.58 5.956 7.007 5.666 6.666 ns 7 none 2.481 2.918 6.281 7.389 5.871 6.907 6.354 7.475 5.944 6.993 ns lvcmos 2.5 v (for msiod i/o bank) 2 none 2.367 2.786 5.054 5.946 4.749 5.587 5.158 6.069 4.853 5.71 ns 3 none 1.978 2.328 5.533 6.509 5.159 6.069 5.637 6.632 5.263 6.192 ns 4 none 1.843 2.169 5.927 6.973 5.495 6.465 6.031 7.096 5.599 6.588 ns 6 none 1.757 2.067 6.33 7.447 5.795 6.818 6.434 7.57 5.899 6.941 ns 8 none 1.77 2.083 6.607 7.773 5.998 7.056 6.711 7.896 6.102 7.179 ns table 2-25 ? lvcmos 2.5 v transmitter ch aracteristics (continued) output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenzh units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std.
smartfusion2 system-on-chip fpgas revision 0 2-27 advance information (s ubject to change) 1.8 v lvcmos lvcmos 1.8 is a general standard for 1.8 v applic ations and is supported in smartfusion2 fpgas in compliance to the jedec specification jesd8-7a. minimum and maximum dc/ac input a nd output levels specification table 2-26 ? lvcmos 1.8 v dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc operating conditions vddi supply voltage 1.710 1.8 1.89 v lvcmos 1.8 v dc input voltage specification vih (dc) dc input logic high for (msiod and ddrio i/o bank) 0.65 * vddi ? 1.89 v vih (dc) dc input logic high (for msio i/o bank) 0.65 * vddi ? 3.45 v vil (dc) dc input logic low ?0.3 ? 0.35 * vddi v iih (dc) input current high ? ? 10 ma iil (dc) input current low ? ? 10 ma lvcmos 1.8 v dc output voltage specification voh dc output logic high vddi ? 0.45 ? ? v vol dc output logic low ? ? 0.45 v lvcmos 1.8 v ac specifications fmax maximum data rate (for ddrio i/o bank) ac loading: 5 pf load, maximum drive/slew ??200mbps fmax maximum data rate (for msio i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ??295mbps fmax maximum data rate (for msiod i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ??320mbps supported output driver calibrated impedance (for ddrio i/o bank) 75, 60, 50, 33, 25, 20 ohms lvcmos 1.8 v ac test parameters specifications vtrip measuring/trip point for data path ? 0.9 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ? 5 ? pf cload capacitive loading for data path (tdp) ? 5 ? pf table 2-27 ? lvcmos 1.8 v transmitter dr ive strength specifications output drive selection voh (v) vol (v) ioh (at voh) ma iol (at vol) ma notes msio i/o bank msiod i/o bank ddrio i/o bank min. max. 2 2 2 vddi ? 0.4 0.45 2 2 3 3 3 vddi ? 0.4 0.45 4 4 4 5 4 vddi ? 0.4 0.45 6 6 5 6 5 vddi ? 0.4 0.45 8 8 6 8 7 vddi ? 0.4 0.45 10 10 7 n/a 8 vddi ? 0.4 0.45 12 12 n/a n/a 10 vddi ? 0.4 0.45 16 16
smartfusion2 dc and switching characteristics 2-28 revision 0 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 1.71 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-28 ? lvcmos 1.8 v receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. lvcmos 1.8 v (for ddrio i/o bank) 0 tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns lvcmos 1.8 v (for msio i/o bank) 0 3.241 3.813 3.248 3.82 ns 50 3.377 3.973 3.381 3.977 ns 75 3.332 3.92 3.342 3.932 ns 150 3.285 3.865 3.297 3.879 ns lvcmos 1.8 v (for msiod i/o bank) 0 tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns table 2-29 ? lvcmos 1.8 v transmi tter characteristics output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvcmos 1.8 v (for ddrio i/o bank) 2 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 4 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-29 advance information (s ubject to change) 5 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 7 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 8 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 10 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns lvcmos 1.8 v (for msio i/o bank) 2 none 3.486 4.101 4.621 5.436 5.10 7 6.008 4.607 5.419 5.093 5.991 ns 3 none 3.244 3.816 5.351 6.295 5.51 8 6.492 5.337 6.278 5.504 6.475 ns 4 none 3.148 3.703 6.32 7.436 5.963 7.015 6.306 7.419 5.949 6.998 ns 5 none 3.189 3.752 8.577 7.738 6.13 1 7.213 6.563 7.721 6.117 7.196 ns 6 none 3.241 3.812 6.956 8.184 6.34 4 7.464 6.942 8.167 6.33 7.447 ns 7 none 3.319 3.904 7.076 8.324 6.44 7.577 7.062 8.307 6.426 7.56 ns lvcmos 1.8 v (for msiod i/o bank) 2 none 2.789 3.282 5.321 6.26 4.98 5.86 5.383 6.333 5.042 5.933 ns 3 none 2.332 2.744 5.846 6.878 5.42 6.377 5.908 6.951 5.482 6.45 ns 5 none 2.1 2.472 6.497 7.644 5.945 6.994 6.559 7.717 6.007 7.067 ns 6 none 2.099 2.47 6.755 7.947 6.14 2 7.227 6.817 8.02 6.204 7.3 ns 8 none 2.136 2.513 7.046 8.29 6.355 7.477 7.108 8.363 6.417 7.55 ns table 2-29 ? lvcmos 1.8 v transmitter ch aracteristics (continued) output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std.
smartfusion2 dc and switching characteristics 2-30 revision 0 advance information (s ubject to change) 1.5 v lvcmos lvcmos 1.5 is a general standard for 1.5 v applicat ions and is supported in smartfusion2 fpgas in compliance to the jedec specification jesd8-11a. minimum and maximum dc/ac input a nd output levels specification table 2-30 ? lvcmos 1.5 v dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.425 1.5 1.575 v lvcmos 1.5 v dc input voltage specification vih (dc) dc input logic high for (msiod and ddrio i/o banks) 0.65 * vddi ? 1.575 v vih (dc) dc input logic high (for msio i/o bank) 0.65 * vddi ? 3.45 v vil (dc) dc input logic low ?0.3 ? 0.35 * vddi v iih (dc) input current high ? ? 10 ma iil (dc input current low ? ? 10 ma lvcmos 1.5 v dc output voltage specification voh dc output logic high vddi * 0.75 ? ? v vol dc output logic low ? ? vddi * 0.25 v lvcmos 1.5 v ac specifications fmax maximum data rate (for ddrio i/o bank) ac loading: 5 pf load, maximum drive/slew ??130mbps fmax maximum data rate (for msio i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ??80mbps fmax maximum data rate (for msiod i/o bank) ac loading: 10 pf / 500 ohm load, maximum drive/slew ??170mbps supported output driver calibrated impedance (for ddrio i/o bank) 75, 60, 50, 40 ohms lvcmos 1.5 v ac test parameters specifications vtrip measuring/trip point ? 0.75 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf cload capacitive loading for data path (tdp) ? 5 ? pf table 2-31 ? lvcmos 1.5 v transmitter dr ive strength specifications output drive selection voh (v) vol (v) ioh (at voh) ma iol (at vol) ma notes msio i/o bank msiod i/o bank ddrio i/o bank min. max. 2 3 2 vddi * 0.75 vddi * 0.25 2 2 4 5 4 vddi * 0.75 vddi * 0.25 4 4 5 7 6 vddi * 0.75 vddi * 0.25 6 6 7 n/a 8 vddi * 0.75 vddi * 0.25 8 8 n/a n/a 10 vddi * 0.75 vddi * 0.25 10 10 n/a n/a 12 vddi * 0.75 vddi * 0.25 12 12
smartfusion2 system-on-chip fpgas revision 0 2-31 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 1.425 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-32 ? lvcmos 1.5 v receiver characteristics tdin tsch_din units on die termination (odt) ?1 std. ?1 std. lvcmos 1.5 v (for ddrio i/o bank) 0 tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns lvcmos 1.5 v (for msio i/o bank) 0 3.817 4.49 3.844 4.522 ns 50 4.13 4.858 4.164 4.898 ns 75 4.01 4.717 4.044 4.757 ns 150 3.916 4.607 3.944 4.64 ns lvcmos 1.5 v (for msiod i/o bank) 0 tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns table 2-33 ? lvcmos 1.5 v transmi tter characteristics output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvcmos 1.5 v (for ddrio i/o bank) 2 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 4 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 6 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-32 revision 0 advance information (s ubject to change) 8 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 10 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 12 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns lvcmos 1.5 v (for msio i/o bank) 2 none 4.437 5.219 5.342 6.285 5.57 6.552 5.295 6.23 5.523 6.497 ns 4 none 3.989 4.692 7.006 8.242 6.488 7.633 6.959 8.187 6.441 7.578 ns 5 none 4.046 4.76 7.288 8.574 6.664 7.839 7.241 8.519 6.617 7.784 ns 7 none 4.226 4.971 7.869 9.257 6.99 8.224 7.822 9.202 6.943 8.169 ns lvcmos 1.5 v (for msiod i/o bank) 3 none 2.788 3.279 6.125 7.206 5.662 6.661 6.179 7.27 5.716 6.725 ns 5 none 2.489 2.927 6.831 8.037 6.24 7.341 6.885 8.101 6.294 7.405 ns 7 none 2.508 2.95 7.212 8.484 6.527 7.679 7.266 8.548 6.581 7.743 ns table 2-33 ? lvcmos 1.5 v transmitter ch aracteristics (continued) output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std.
smartfusion2 system-on-chip fpgas revision 0 2-33 advance information (s ubject to change) 1.2 v lvcmos lvcmos 1.2 is a general standard for 1.2 v applicat ions and is supported in smartfusion2 fpgas in compliance to the jedec specification jesd8-12a. lvcmos 1.2 v minimum and maximum dc/ac input and output levels specification table 2-34 ? lvcmos 1.2 v dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.14 1.2 1.26 v lvcmos 1.2 v dc input voltage specification vih (dc) dc input logic high for (msiod and ddrio i/o bank) 0.65 * vddi ? 1.26 v vih (dc) dc input logic high (for msio i/o bank) 0.65 * vddi ? 3.45 v vil (dc) dc input logic low ?0.3 ? 0.35 * vddi v iih (dc) input current high ? ? 10 ma iil (dc) input current low ? ? 10 ma lvcmos 1.2 v dc output voltage specification voh dc output logic high vddi * 0.75 ? ? v vol dc output logic low ? ? vddi * 0.25 v lvcmos 1.2 v ac specifications fmax maximum data rate (for ddrio i/o bank) ac loading: 2 pf load, maximum drive/slew ??75mbps fmax maximum data rate (for msio i/o bank) ac loading: 2.5 pf load, maximum drive/slew ??50mbps fmax maximum data rate (for msiod i/o bank) ac loading: 2.5 pf load, maximum drive/slew ??100mbps rref supported output driver calibrated impedance (for ddrio i/o bank) 75, 60, 50, 40 ohms lvcmos 1.2 v ac test parameters specifications vtrip measuring/trip point ? 0.6 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ? 5 ? pf cload capacitive loading for data path (tdp) ? 5 ? pf table 2-35 ? lvcmos 1.2 v transmitter dr ive strength specifications output drive selection voh (v) vol (v) ioh (at voh) ma iol (at vol) ma notes msio i/o bank msiod i/o bank ddrio i/o bank min. max. 4 4 4 vddi * 0.75 vddi * 0.25 2 2 7 8 8 vddi * 0.75 vddi * 0.25 4 4 n/a n/a 12 vddi * 0.75 vddi * 0.25 6 6
smartfusion2 dc and switching characteristics 2-34 revision 0 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 1.14 v ac switching characteristics fo r receiver (input buffers)) table 2-36 ? lvcmos 1.2 v receiver characteristics on die termination (odt) tdin tsch_din ?1 std. ?1 std. units lvcmos 1.2 v (for ddrio i/o bank) 0 tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns lvcmos 1.2 v (for msio i/o bank) 0 5.3 6.235 5.335 6.276 ns 50 6.776 7.971 6.836 8.042 ns 75 6.179 7.269 6.23 7.32 ns 150 5.683 6.686 5.73 6.741 ns lvcmos 1.2 v (for msiod i/o bank) 0 tbd tbd tbd tbd ns 50 4.639 5.458 4.676 5.502 ns 75 5.599 6.588 5.66 6.66 ns 150 5.037 5.926 5.081 5.978 ns
smartfusion2 system-on-chip fpgas revision 0 2-35 advance information (s ubject to change) ac switching characteristics for transm itter (output and tristate buffers) table 2-37 ? lvcmos 1.2 v transmi tter characteristics output drive selection slew control (0 lowest, 3 highest) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvcmos 1.2 v (for ddrio i/o bank) 4 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 8 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 12 0 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 1 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 2 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns 3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns lvcmos 1.2 v (for msio i/o bank) 4 none 5.87 6.905 8.659 10.186 7.563 8.897 8.53 10.035 7.434 8.746 ns 7 none 6.215 7.312 9.639 11.339 8.114 9.546 9.51 11.188 7.985 9.395 ns lvcmos 1.2 v (for msiod i/o bank) 4 none 3.509 4.128 7.29 8.577 6.693 7.874 7.356 8.654 6.759 7.951 ns 8 none 3.419 4.022 8.135 9.571 7.347 8.644 8.201 9.648 7.413 8.721 ns
smartfusion2 dc and switching characteristics 2-36 revision 0 advance information (s ubject to change) 3.3 v pci/pcix peripheral component interface (pci) for 3.3 v standards specifies support for 33 mhz and 66 mhz pci bus applications. minimum and maximum dc/ac input a nd output levels specification table 2-38 ? pci/pcix dc voltage specification ? applicable to msio bank only symbols parameters conditions min. typ. max. units notes pci/pcix recommended dc operating conditions vddi supply voltage 3.15 3.3 3.45 v pci/pcix dc input voltage specification vi dc input voltage 0 ? 3.45 v iih(dc) input current high ? ? 10 a iil(dc) input current low ? ? 10 a pci/pcix dc output voltage specification voh dc output logic high per pci specification v vol dc output logic low per pci specification v pci/pcix ac specifications fmax maximum data rate (msio i/o bank) ac loading: per jedec specifications ? ? 630 mbps pci/pcix ac test para meters specifications vtrip measuring/trip point for data path (falling edge) ? 0.615 * vddi ? v vtrip measuring/trip point for data path (rising edge) ? 0.285 * vddi ? v rtt_test resistance for data test path ? 25 ? ohms rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-37 advance information (s ubject to change) ac switching characteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 3.0 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-39 ? ac switching characteristics for receiver (input buffers) on die termination (odt) tdin tsch_din units speed grade speed grade ? std. ?1 std. pci/pcix (for msio i/o bank) none 2.266 2.667 2.25 2.648 ns table 2-40 ? ac switching characteristics for tran smitter (output an d tristate buffers tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. pci/pcix (for msio i/o bank) tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-38 revision 0 advance information (s ubject to change) memory interface and voltag e referenced i/o standards high-speed transceiver logic (hstl) the high-speed transceiver logic (hstl) standard is a general purpose high-speed bus standard sponsored by ibm (eia/jesd8-6). smartfusion2 devic es support two classes of the 1.5 v hstl. these differential versions of the st andard require a differential amplif ier input buffer and a push-pull output buffer. minimum and maximum dc/ac input a nd output levels specification table 2-41 ? hstl dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.425 1.5 1.575 v vtt termination voltage 0.698 0.750 0.803 v vref input reference voltage 0.698 0.750 0.803 v hstl dc input voltage specification vih (dc) dc input logic high vref + 0.1 ? 1.575 v vil (dc) dc input logic low ?0.3 ? vref ? 0.1 v iih (dc) input current high ? ? 10 v iil (dc) input current low ? ? 10 v hstl dc output voltage specification hstl class i voh dc output logic high vddi ? 0.4 ? ? v vol dc output logic low ? ? 0.4 v ioh at voh output minimum source dc current (msiod i/o bank) ?7.8 ? ? ma 1 iol at vol output minimum sink current (msiod i/o bank) 7.8 ? ? ma 1 ioh at voh output minimum source dc current (msio and ddrio i/o banks) ?8.0 ? ? ma iol at vol output minimum sink current (msio and ddrio i/o banks) 8.0 ? ? ma hstl class ii (applicable to msio and ddrio io bank only) voh dc output logic high vddi ? 0.4 ? ? v vol dc output logic low ? ? 0.4 v ioh at voh output minimum source dc current ?16.0 ? ? ma iol at vol output minimum sink current 16.0 ? ? ma hstl ac/dc differential voltage specifications vid (dc) dc input differential voltage 0.2 ? ? v vdiff (ac) ac input differential voltage 0.4 ? ? v vx (ac) ac differential cross point voltage 0.68 ? 0.9 v hstl ac specifications fmax maximum data rate (ddrio i/o bank) ac loading: per jedec specifications ? ? 800 mbps fmax maximum data rate (for msio i/o bank) ac loading: 3 pf / 50 ohm load ? ? 140 mbps notes: 1. msiod i/o bank hstl class i does not meet standard jedec test point. use provided lower current values as specified.
smartfusion2 system-on-chip fpgas revision 0 2-39 advance information (s ubject to change) fmax maximum data rate (for msiod i/o bank) ac loading: 3 pf / 50 ohm load ? ? 180 mbps rref supported output driver calibrated impedance (for ddrio i/o bank) reference resistance = 191 ohms ? 25.5, 47.8 ?ohms rtt effective impedance value (with respect to reference resistor of 191 ohms) (odt for ddrio i/o bank only) reference resistance = 191 ohms ? 47.8 ? ohms rtt effective impedance value (odt for msio and msiod i/o banks only) reference resistance = 191 ohms ? 50, 75, 150 ?ohms hstl ac test parame ters specification vtrip measuring/trip point for data path ? ? ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf rtt_test reference resistance for data test path for sstl15 class i (tdp) 50 ohms rtt_test reference resistance for data test path for sstl15 class ii (tdp) ?25?ohms cload capacitive loading for data path (tdp) ? 5 ? pf table 2-41 ? hstl dc voltage specification (continued) symbols parameters conditions min. typ. max. units notes notes: 1. msiod i/o bank hstl class i does not meet standard jedec test point. use provided lower current values as specified.
smartfusion2 dc and switching characteristics 2-40 revision 0 advance information (s ubject to change) ac switching ch aracteristics ac switching characteristics for receiver (input buffers) table 2-42 ? hstl receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. hstl (for ddrio i/o bank) pseudo-differential none tbd tbd n/a n/a ns 47.8 tbd tbd n/a n/a ns true-differential none tbd tbd n/a n/a ns 47.8 tbd tbd n/a n/a ns hstl (for msio i/o bank) pseudo-differential none 13. 8 16.236 18.906 22.242 ns 50 13.65 16.059 19.056 22.419 ns 75 13.637 16.044 19.02 22.377 ns 150 13.597 15.996 18.964 22.31 ns true-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns hstl (for msiod i/o bank) pseudo-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns true-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-41 advance information (s ubject to change) ac switching characteristics for transm itter (output and tristate buffers) table 2-43 ? hstl transmitter characteristics tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. hstl class i for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msiod i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns hstl class ii for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-42 revision 0 advance information (s ubject to change) stub-series terminated logic stub-series terminated logic (sstl) for 2.5 v (sstl2), 1.8 v (sstl18), and 1.5 v (sstl15) is supported in smartfusion2 devices. sstl2 is def ined by jedec standard jesd8-9b and sstl18 is defined by jedec standard jesd8-15. smartfusion2 sstl i/o configurations are designed to meet double data rate standards ddr/2/3 for general purpos e memory buses. double data rate standards are designed to meet their jedec specifications as defined by jedec standard jesd79f for ddr, jedec standard jesd79-2f for ddr, jedec standard j esd79-3d for ddr3 and jedec standard jesd209a for lpddr. stub-series terminated logic 2.5 v (sstl2) sstl2 class i and class ii are supported in smartfus ion2 devices, and also comply with reduced and full drive of double data rate (ddr) standards. smartfusion2 fpga i/o supports both standards for single-ended signaling and differential signaling for sst l2. this standard requires a differential amplifier input buffer and a push-pull output buffer. minimum and maximum dc/ac input a nd output levels specification table 2-44 ? ddr1/sstl2 dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 2.625 v vtt termination voltage 1.164 1.250 1.339 v vref input reference voltage 1.164 1.250 1.339 v ddr/sstl2 dc input vo ltage specification vih (dc) dc input logic high vref + 0.125 ? 2.625 v vil (dc) dc input logic low ?0.3 ? vref ? 0.15 v iih (dc) input current high ? ? 10 a iil (dc) input current lo ? ? 10 a ddr/sstl2 dc output voltage specification sstl2 class i (ddr reduced drive) voh dc output logic high vtt + 0.608 ? ? v vol dc output logic low ? ? vtt ? 0.608 v ioh at voh output minimum source dc current 8.1 ? ? ma iol at vol output minimum sink current ?8.1 ? ? ma sstl2 class ii (ddr full drive) ? appl icable to msio and ddrio i/o banks only voh dc output logic high vtt + 0.81 ? ? v vol dc output logic low ? ? vtt ? 0.81 v ioh at voh output minimum source dc current 16.2 ? ? ma iol at vol output minimum sink current ?16.2 ? ? ma sstl2 ac/dc differential voltage specification vid (dc) dc input differential voltage 0.3 ? ? v vdiff (ac) ac input differential voltage 0.7 ? ? v vx (ac) ac differential cross point voltage 0.5 * vddi ? 0.2 ? 0.5 * vddi + 0.2 v
smartfusion2 system-on-chip fpgas revision 0 2-43 advance information (s ubject to change) sstl2 ac specifications fmax maximum data rate (for ddrio i/o bank) ac loading: per jedec specifications ? ? 400 mbps fmax maximum data rate (for msio i/o bank) ac loading: 10 pf / 50 ohm load ? ? 575 mbps fmax maximum data rate (for msiod i/o bank) ac loading: 30 pf / 50 ohm load ? ? 700 mbps rref supported output driver calibrated impedance (for ddrio i/o bank) reference resistor = 150 ohms ? 20, 42 ? ohms ac test parameters specifications vtrip measuring/trip point for data path ? 1.25 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ?5?pf rs series resistance for data test path (tdp) ? 25 ? ohms rtt_test reference resistance for data test path for sstl2 class i (tdp) ?50?ohms rtt_test reference resistance for data test path for sstl2 class ii (tdp) ?25?ohms cload capacitive loading for data path (tdp) ? 5 ? pf table 2-44 ? ddr1/sstl2 dc voltage specification (continued) symbols parameters conditions min. typ. max. units notes
smartfusion2 dc and switching characteristics 2-44 revision 0 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-45 ? ddr1/sstl2 receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. sstl2 (for ddrio i/o bank) pseudo-differential none tbd tbd ? ? ns true-differential none tbd tbd ? ? ns sstl2 (for msio i/o bank) pseudo-differential none 2.805 3.3 2.987 3.515 ns true-differential none tbd tbd tbd tbd ns sstl2 (for msiod i/o bank) pseudo-differential none tbd tbd tbd tbd ns true-differential none tbd tbd tbd tbd ns table 2-46 ? ddr1/sstl2 transmitter characteristics tdout tenzl tenzh tenhz tenlz ?1 std ?1 std ?1 std ?1 std ?1 std units sstl2 class i for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msiod i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns sstl2 class ii for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msiod i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-45 advance information (s ubject to change) stub-series terminated logic 1.8 v (sstl18) sstl18 class i and class ii are supported in smar tfusion2 devices, and also comply with the reduced and full drive double date rate (ddr2) standard. smartfusion2 fpga i/o supports both standards for single-ended signaling and differential signaling for sstl18. this standard requires a differential amplifier input buffer and a push-pull output buffer. minimum and maximum dc/ac input a nd output levels specification table 2-47 ? sstl18 dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.71 1.8 1.89 v vtt termination voltage 0.838 0.900 0.964 v vref input reference voltage 0.838 0.900 0.964 v sstl18 dc input voltage specification vih (dc) dc input logic high vref + 0.125 ? 1.89 v vil (dc) dc input logic low ?0.3 ? vref ? 0.125 v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a sstl18 dc output voltage specification sstl18 class i (ddr2 reduced drive) voh dc output logic high vtt + 0.603 ? ? v vol dc output logic low ? ? vtt? 0.603 v ioh at voh output minimum source dc current (msio i/o bank only 4.7 ? ? ma 1 iol at vol output minimum si nk current (msio i/o bank only) ?4.7 ? ? ma 1 ioh at voh output minimum source dc current (msiod i/o bank only 6.3 ? ? ma 1 iol at vol output minimum si nk current (msiod i/o bank only) ?6.3 ? ? ma 1 ioh at voh output minimum source dc current (ddrio i/o bank only 6.5 ? ? ma 1 iol at vol output minimum si nk current (ddrio i/o bank only) ?6.5 ? ? ma 1 notes: 1. msio i/o bank sstl18/ddr2 reduced drive does not have a st andard test point. this is defined to fit within the ddr2 reduced drive iv curve minimums. 2. msio i/o bank sstl18/ddr2 class ii does not meet the st andard jedec test points. use provided lower current values as specified.
smartfusion2 dc and switching characteristics 2-46 revision 0 advance information (s ubject to change) stl18 class ii (ddr2 full drive) ? applicable to msio and ddrio i/o banks only voh dc output logic high vtt + 0.603 ? ? v vol dc output logic low ? ? vtt? 0.603 v ioh at voh output minimum so urce dc current (msio i/o bank only) 9.3 ? ? ma iol at vol output minimum si nk current (msio i/o bank only) ?9.3 ? ? ma ioh at voh output minimum s ource dc current (ddrio i/o bank only) 13.4 ? ? ma iol at vol output minimum si nk current (ddrio i/o bank only) ?13.4 ? ? ma sstl18 ac/dc differential voltage specification vid (dc dc input differential voltage 0.3 ? ? v vdiff (ac) ac input differential voltage 0.7 v vx (ac) ac differential cross point voltage 0.5 * vddi ? 0.175 ? 0.5 * vddi + 0.175 v sstl18 ac specification fmax maximum data rate (for ddrio i/o bank) ac loading: per jedec specification ??800mbps fmax maximum data rate (for msio i/o bank) ac loading: 3 pf / 25 ohm load ??432mbps fmax maximum data rate (for msiod i/o bank) ac loading: 3 pf / 25 ohm load ??430mbps rref supported output driver calibrated impedance (for ddrio i/o bank) reference resistor = 150 ohms ?20, 42 ohms rtt effective impedance value (with respect to reference resistor 150 ohms) (odt for ddrio i/o bank only) reference resistor = 150 ohms ? 50, 75, 150 ohms table 2-47 ? sstl18 dc voltage specification (continued) symbols parameters conditions min. typ. max. units notes notes: 1. msio i/o bank sstl18/ddr2 reduced drive does not have a st andard test point. this is defined to fit within the ddr2 reduced drive iv curve minimums. 2. msio i/o bank sstl18/ddr2 class ii does not meet the st andard jedec test points. use provided lower current values as specified.
smartfusion2 system-on-chip fpgas revision 0 2-47 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 1.71 v ac switching characteristics for receiver (input buffers) ac test parameters specifications vtrip measuring/trip point for data path ? 0.9 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ?5?pf rs series resistance for data test path (tdp) ? 25 ? ohms rtt_test reference resistance for data test path for sstl18 class i (tdp) ?50?ohms rtt_test reference resistance for data test path for sstl18 class ii (tdp) ?25?ohms cload capacitive loading for data path (tdp) ? 5 ? pf table 2-47 ? sstl18 dc voltage specification (continued) symbols parameters conditions min. typ. max. units notes notes: 1. msio i/o bank sstl18/ddr2 reduced drive does not have a st andard test point. this is defined to fit within the ddr2 reduced drive iv curve minimums. 2. msio i/o bank sstl18/ddr2 class ii does not meet the st andard jedec test points. use provided lower current values as specified. table 2-48 ? ddr2/sstl18 receiver characteristics odt (on die termination) tdin tsch_din units ?1 std ?1 std sstl18 (for ddrio i/o bank) pseudo-differential none tbd tbd n/a n/a ns 50 tbd tbd n/a n/a ns 75 tbd tbd n/a n/a ns 150 tbd tbd n/a n/a ns true-differential none tbd tbd n/a n/a ns 50 tbd tbd n/a n/a ns 75 tbd tbd n/a n/a ns 150 tbd tbd n/a n/a ns sstl18 (for msio i/o bank) pseudo-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-48 revision 0 advance information (s ubject to change) ac switching characteristics for transm itter (output and tristate buffers) true-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns sstl18 (for msiod i/o bank) pseudo-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns true-differential none tbd tbd tbd tbd ns 50 tbd tbd tbd tbd ns 75 tbd tbd tbd tbd ns 150 tbd tbd tbd tbd ns table 2-48 ? ddr2/sstl18 receiver characteristics odt (on die termination) tdin tsch_din units ?1 std ?1 std table 2-49 ? ddr2/sstl18 transmitter characteristics tdout tenzl tenzh tenhz tenlz units ?1 std ?1 std ?1 std ?1 std ?1 std sstl2 class i for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msiod i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns sstl2 class ii for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns for msiod i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-49 advance information (s ubject to change) stub-series terminated logic 1.5 v (sstl15) sstl15 class i and class ii are supported in smar tfusion2 devices, and also comply with the reduced and full drive double data rate (ddr3) standard. smartfusion2 fpga i/o supports both standards for single-ended signaling and differential signaling for sstl18. this standard requires a differential amplifier input buffer and a push-pull output buffer. minimum and maximum dc/ac input a nd output levels specification table 2-50 ? sstl15 dc voltage specification (for ddrio i/o bank only) symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.425 1.5 1.575 v vtt termination voltage 0.698 0.750 0.803 v vref input reference voltage 0.698 0.750 0.803 v sstl15 dc input voltage specification vih(dc) dc input logic high vref + 0.1 ? 1.575 v vil(dc) dc input logic low ?0.3 ? vref ? 0.1 v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a sstl15 dc output voltage specification ddr3/sstl15 class i ( ddr3 reduced drive) voh dc output logic high 0.8 * vddi ? ? v vol dc output logic low ? ? 0.2 * vddi v ioh at voh output minimum source dc current 6.5 ? ? ma iol at vol output minimu m sink current ?6.5 ? ? ma sstl15 class ii (ddr3 full drive) voh dc output logic high 0.8 * vddi ? ? v vol dc output logic low ? - 0.2 * vddi v ioh at voh output minimum source dc current 7.6 ? ? ma iol at vol output minimu m sink current ?7.6 ? ? ma sstl15 differential voltage specification vid (dc) dc input differential voltage 0.2 ? ? v vdiff (ac) ac input differential voltage 0.7 ? ? v vx (ac) ac differential cross point voltage 0.5 * vddi ? 0.150 ?0.5 * vddi + 0.150 v
smartfusion2 dc and switching characteristics 2-50 revision 0 advance information (s ubject to change) sstl15 ac specification fmax maximum data rate (for ddrio i/o bank) ac loading: per jedec specifications 800 mbps rref supported output driver calibrated impedance reference resistor = 240 ohms 34, 40 ohms rtt effective impedance value (with respect to reference resistor 240 ohms) (odt for ddrio i/o bank only) reference resistor = 240 ohms 20, 30, 40, 60, 120 ohms ac test parameters specifications vtrip measuring/trip point for data path ? 0.75 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ?5?pf rs series resistance for data test path (tdp) ? 25 ? ohms rtt_test reference resistance for data test path for sstl15 class i (tdp) ?50?ohms rtt_test reference resistance for data test path for sstl15 class ii (tdp) ?25?ohms cload capacitive loading for data path (tdp) ? 5 ? pf table 2-50 ? sstl15 dc voltage specification (for ddrio i/o bank only) (continued) symbols parameters conditions min. typ. max. units notes
smartfusion2 system-on-chip fpgas revision 0 2-51 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 1.425 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-51 ? sstl15 receiver characteristics on die termination (odt) tdin ?1 std. units ddr3/sstl15 (for ddrio i/o bank) pseudo-differential none tbd tbd ns 20 tbd tbd ns 30 tbd tbd ns 40 tbd tbd ns 60 tbd tbd ns 120 tbd tbd ns true-differential none tbd tbd ns 20 tbd tbd ns 30 tbd tbd ns 40 tbd tbd ns 60 tbd tbd ns 120 tbd tbd ns table 2-52 ? ddr3/sstl15 transmitter characteristics tdout tenzl tenzh tenhz tenlz ?1 std ?1 std ?1 std ?1 std ?1 std units ddr3 reduced driv e/sstl15 class i for ddrio i/o bank single ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns ddr3 full drivesstl15 class ii for ddrio io bank single ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-52 revision 0 advance information (s ubject to change) low power double data rate (lpddr) lpddr reduced and full drive low power double data rate standards are supported in smartfusion2 fpga i/os. this standard requires a differential amplifier input buffer and a push-pull output buffer. minimum and maximum dc/ac input a nd output levels specification table 2-53 ? lpddr dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 1.71 1.8 1.89 v vtt termination voltage 0.838 0.900 0.964 v vref input reference voltage 0.838 0.900 0.964 v lpddr dc input voltage specification vih (dc) dc input logic high 0.3 * vddi ? 1.89 v vil (dc) dc input logic low ?0.3 ? 0.7 * vddi v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a lpddr dc output voltage specification voh dc output logic high 0.9 * vddi ? ? v vol dc output logic low ? ? 0.1 * vddi v ioh at voh output minimum source dc current 0.1 ? ? ma iol at vol output minimum sink current ?0.1 ? ? ma lpddr differential voltage specification vid (dc) dc input differential voltage 0.4 * vddi ? ? v vdiff (ac) ac input differen tial voltage 0.6 * vddi v vx (ac) ac differential cross point voltage 0.4 * vddi ? 0.6 * vddi v lpddr ac specifications fmax maximum data rate ac loading: per jedec specifications mbps rref supported output driver calibrated impedance reference resistor = 150 ohms 20, 42 ohms rtt effective impedance value ? odt reference resistor = 150 ohms 50, 70, 150 ohms ac test parameters specifications vtrip measuring/trip point for data path ? 0.9 ? v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ?5 ?pf rs series resistance for data test path (tdp) ? 25 ? ohms rtt_test reference resistance for data test path for lpddr (tdp) ?50 ?ohms cload capacitive loading for data path (tdp) ? 5 ? ohms
smartfusion2 system-on-chip fpgas revision 0 2-53 advance information (s ubject to change) ac switching ch aracteristics table 2-54 ? lpddr receiver characteristics on die termination (odt) tdin units ?1 std. lpddr (for ddrio i/o bank) pseudo-differential none tbd tbd ns true-differential none tbd tbd ns 50 tbd tbd ns 75 tbd tbd ns 150 tbd tbd ns table 2-55 ? lpddr transmitter characteristics tdout tenzl tenzh tenhz tenlz ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. units lpddr reduced drive for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns lpddr full drive for ddrio i/o bank single-ended tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns differential tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-54 revision 0 advance information (s ubject to change) differential i/o standards configuration of the i/o modules as a differential pair is handled by soc products group libero software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output regist er (outreg), enable register (enreg), and double data rate registers (ddr). lvds low-voltage differential signaling (ansi/tia/eia-644) is a high-speed, differential i/o standard. minimum and maximum input and output levels table 2-56 ? lvds dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 3.45 v lvds dc input voltage specification vi dc input voltage 0 ? 2.925 v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a lvds dc output voltage specification voh dc output logic high 1.25 1.425 1.6 v vol dc output logic low 0.9 1.075 1.25 v lvds differential voltage specification vod differential output voltage swing 250 350 450 mv vocm output common mode voltage 1.125 1.25 1.375 v vicm input common mode voltage 0.05 1.25 1.375 v vid input differential voltage 100 350 600 mv lvds ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 2 pf / 100 ohm differential load ? ? 535 mbps fmax maximum data rate (for msiod i/o bank) ? no pre-emphasis ac loading: 2 pf / 100 ohm differential load 700 730 750 mbps fmax maximum data rate (for msiod i/o bank) ? min. pre-emphasis ac loading: 2 pf / 100 ohm differential load 970 1200 1270 mbps fmax maximum data rate (for msiod io bank) ? max. pre-emphasis ac loading: 2 pf / 100 ohm differential load 1000 1500 1700 mbps rt termination resistance ? 100 ? ohms ac test parameters specifications vtrip measuring/trip point for data path ? cross point ?v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable path (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-55 advance information (s ubject to change) ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-57 ? lvds receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. lvds (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns lvds (for msiod i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns table 2-58 ? lvds transmitter characteristics tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. lvds (for msio i/o bank) tbdtbdtbdtbdtbdtbdtbdtbdtbdtbd ns lvds (for msiod i/o bank) no pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns min. pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns max. pre-emphasis tbdtbdtbdtbdtbdtbdtbdtbdtbdtbd ns
smartfusion2 dc and switching characteristics 2-56 revision 0 advance information (s ubject to change) b-lvds bus lvds (b-lvds) specifications extend the exis ting lvds standard to high-performance multipoint bus applications. multidrop and multipoint bus conf igurations may contain any combination of drivers, receivers, and transceivers. minimum and maximum dc/ac input a nd output levels specification table 2-59 ? b-lvds dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 2.625 v bus lvds dc input voltage specification vi dc input voltage 0 ? 2.925 v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a bus lvds dc output voltage spec ification (for msio i/o bank only) voh dc output logic high 1.25 1.425 1.6 v vol dc output logic low 0.9 1.075 1.25 v bus lvds differential voltage specification vod differential output volt age swing (for msio i/o bank only) 240 ? 460 mv vocm output common mode voltage (for msio i/o bank only) 1.1 ? 1.5 v vicm input common mode voltage 0.05 ? 2.4 ? vid/2 v vid input differential voltage 100 ? 2 * vddi mv bus lvds ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 2 pf / 100 ohm differential load ? ? 500 mbps fmax maximum data rate (for msiod i/o bank, receiver only) ? ? ? mbps rt termination resistance ? 27 ? ohms bus lvds ac test parameters specifications vtrip measuring/trip point for data path ? cross point ?v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-57 advance information (s ubject to change) ac switching characteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-60 ? ac switching characteristics for receiver (input buffers) on die termination (odt) tdin tsch_din units speed grade speed grade ?1 std. ?1 std. bus lvds (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns bus lvds (for msiod i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns table 2-61 ? ac s witching characteristic s for transmitter (output and tristate buffers tdout tenzl tenzh tenhz tenlz ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. units bus-lvds (for msio i/o bank) tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-58 revision 0 advance information (s ubject to change) m-lvds mlvds specifications extend the existing lvds standard to high-performance multipoint bus applications. multidrop and multipoi nt bus configurations may cont ain any combination of drivers, receivers, and transceivers. minimum and maximum input and output levels table 2-62 ? m-lvds dc voltage specification symbols parameters conditions min. typ. max. units notes m-lvds recommended dc operating conditions vddi supply voltage 2.375 2.5 2.625 v m-lvds dc input voltage specification vi dc input voltage 0 ? 2.925 v iih (dc) input current high ? ? 10 a iil (dc) input current low ? ? 10 a m-lvds dc output voltage specification (for msio io bank only) voh dc output logic high 1.25 1.425 1.6 v vol dc output logic low 0.9 1.075 1.25 v m-lvds differential voltage specification vod differential output voltage swing (for msio i/o bank only) 480 ? 650 mv vocm output common mode voltage (for msio i/o bank only) 0.3 ? 2.1 v vicm input common mode voltage 0.3 ? 1.2 v vid input differential voltage 50 ? 2400 mv m-lvds ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 2 pf / 100 ohm differential load ? ? 500 mbps rt termination resistance ? 50 ? ohms m-lvds ac test parameters specifications vtrip measuring/trip point for data path ? cross point ?v rent resistance for enable path (t zh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-59 advance information (s ubject to change) ac switching characteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-63 ? ac switching characteristics for receiver (input buffers) on die termination (odt) tdin tsch_din units speed grade speed grade ?1 std. ?1 std. mlvds (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns mlvds (for msiod i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns table 2-64 ? ac switching characteristics for transm itter (output and tristate buffers) tdout tenzl tenzh tenhz tenlz ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. units m-lvds (for msio i/o bank) tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-60 revision 0 advance information (s ubject to change) mini-lvds mini-lvds is an unidirectional interface from the ti ming controller to the column drivers and is designed to the texas instruments standard slda007a. mini-lvds minimum and maximum input and output levels table 2-65 ? mini-lvds dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 2.625 v mini-lvds dc input voltage specification vi dc input voltage 0 ? 2.925 v mini-lvds dc output voltage specification voh dc output logic high 1.25 1.425 1.6 v vol dc output logic low 0.9 1.075 1.25 v mini-lvds differential voltage specification vod differential output voltage swing 300 ? 600 mv vocm output common mode voltage 1 ? 1.4 v vicm input common mode voltage 0.3 ? 1.2 v vid input differential voltage 200 ? 600 mv mini-lvds ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 2 pf / 100 ohm differential load ? ?520mbps fmax maximum data rate (for msiod i/o bank, no pre-emphasis) ac loading: 2 pf / 100 ohm differential load 700 725 740 mbps fmax maximum data rate (for msiod i/o bank) ? min. pre-emphasis ac loading: 2 pf / 100 ohm differential load 700 735 750 mbps fmax maximum data rate (for msiod i/o bank) ? med. pre-emphasis ac loading: 2 pf / 100 ohm differential load 970 1,200 1,280 mbps fmax maximum data rate (for msiod i/o bank) ? max. pre-emphasis ac loading: 2 pf / 100 ohm differential load 1,000 1,500 1,700 mbps rt termination resistance 50 150 ohms mini-lvds ac test parameters specifications vtrip measuring/trip point for data path ? cross point ?v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-61 advance information (s ubject to change) ac switching characteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-66 ? ac switching characteristics for receiver (input buffers) on die termination (odt) tdin tsch_din units speed grade speed grade ?1 std. ?1 std. mini-lvds (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns mini-lvds (for msiod i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns table 2-67 ? ac switching characteristics for transm itter (output and tristate buffers) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. mini-lvds (for msio i/o bank) tbdtbdtbdtbdtbdtbdtbdtbdtbdtbd ns mini-lvds (for ms iod i/o bank) no pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns min. pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns max. pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-62 revision 0 advance information (s ubject to change) rsds reduced swing differential signaling (rsds) is similar to an lvds high-speed interface using differential signaling. rsds has a similar implementation to lvds devices and is only intended for point- to-point applications. minimum and maximum input and output levels table 2-68 ? rsds dc voltage specification symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 2.375 2.5 2.625 v rsds dc input voltage specification vi dc input voltage 0 ? 2.925 v rsds dc output voltage specification voh dc output logic high 1.25 1.425 1.6 v vol dc output logic low 0.9 1.075 1.25 v rsds differential voltage specification vod differential output voltage swing 100 ? 600 mv vocm output common mode voltage 0.5 ? 1.5 v vicm input common mode voltage 0.3 ? 1.5 v vid input differential voltage 100 ? 2 * vddi mv rsds ac specifications fmax maximum data rate (for msio i/o bank) ac loading: 2 pf / 100 ohm differential load ? ?520mbps fmax maximum data rate (for msiod i/o banks, no pre-emphasis) ac loading: 2 pf / 100 ohm differential load 700 725 740 mbps fmax maximum data rate (for msiod i/o banks) ? min. pre-emphasis ac loading: 2 pf / 100 ohm differential load 700 735 750 mbps fmax maximum data rate (for msiod i/o banks) ? med. pre-emphasis ac loading: 2 pf / 100 ohm differential load 970 1200 1,280 mbps fmax maximum data rate (for msiod i/o banks) ? max. pre-emphasis) ac loading: 2 pf / 100 ohm differential load 1,000 1,500 1,700 mbps rt termination resistance 100 ohms ac test parameters specifications vtrip measuring/trip point for data path ? cross point ?v rent resistance for enable path (tzh, tzl, thz, tlz) ? 2k ? ohms cent capacitive loading for enable pa th (tzh, tzl, thz, tlz) ? 5 ? pf
smartfusion2 system-on-chip fpgas revision 0 2-63 advance information (s ubject to change) ac switching characteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) ac switching characteristics for transm itter (output and tristate buffers) table 2-69 ? ac switching characteristics for receiver (input buffers) on die termination (odt) tdin tsch_din units speed grade speed grade ?1 std. ?1 std. rsds (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns rsds (for msiod i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns table 2-70 ? ac switching characteristics for transm itter (output and tristate buffers) tdout tenzl tenzh tenhz tenlz units ?1 std. ?1 std. ?1 std. ?1 std. ?1 std. rsds (for msio i/o bank) tbdtbdtbdtbdtbdtbdtbdtbdtbdtbd ns rsds (for msiod i/o bank) no pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns min. pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns max. pre-emphasis tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
smartfusion2 dc and switching characteristics 2-64 revision 0 advance information (s ubject to change) lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit be carried through two signal lines. similar to lvds, two pins are needed. it also requires external resistor termi nation. smartfusion2 devices supp ort only lvpecl receivers and do not support lvpecl transmitters. minimum and maximum input and output levels ac switching ch aracteristics worst commercial-case conditions: t j = 85c, vdd = 1.14 v, vddi = 2.375 v ac switching characteristics for receiver (input buffers) table 2-71 ? lvpecl dc voltage specification ? applicable to msio i/o banks only symbols parameters conditions min. typ. max. units notes recommended dc oper ating conditions vddi supply voltage 3.15 3.3 3.45 v lvpecl dc input voltage specification vih (dc) dc input logic high ? ? 2.3 v vil (dc) dc input logic low 1.6 ? ? v lvpecl differential voltage specification vicm input common mode voltage 0.3 2.8 v vidiff input differential voltage 100 300 1,000 mv other specifications fmax maximum data rate (for msio i/o bank) ? ? 900 mbps table 2-72 ? lvpecl receiver characteristics on die termination (odt) tdin tsch_din units ?1 std. ?1 std. lvpecl (for msio i/o bank) none tbd tbd tbd tbd ns 100 tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-65 advance information (s ubject to change) i/o register specifications input register table 2-73 ? input data enable register propagation delays worst commercial-case conditions: t j = 85c, vdd = 1.14 v parameter description measuring nodes (from, to)* ?1 std. units ticlkq clock-to-q of the input data register tbd tbd ns tisud data setup time for the input data register tbd tbd ns tihd data hold time for the input data register tbd tbd ns tisue enable setup time for th e input data register tbd tbd ns tihe enable hold time for the input data register tbd tbd ns ticlr2q asynchronous clear-to-q of the input data register tbd tbd ns tipre2q asynchronous preset-to-q of the input data register tbd tbd ns tiremclr asynchronous clear removal time for the input data register tbd tbd ns tirecclr asynchronous clear recovery time for the input data register tbd tbd ns tirempre asynchronous preset removal ti me for the input data register tbd tbd ns tirecpre asynchronous preset recovery ti me for the input data register tbd tbd ns tiwclr asynchronous clear minimum pulse width for the input data register tbd tbd ns tiwpre asynchronous preset minimu m pulse width for the input data register tbd tbd ns tickmpwh clock minimum pulse width high for the input data register tbd tbd ns tickmpwl clock minimum pulse width low for the input data register tbd tbd ns *for the derating values at specific junction temperature and voltage supply levels, refer to table 2-11 on page 2-14 for derating values.
smartfusion2 dc and switching characteristics 2-66 revision 0 advance information (s ubject to change) output/enable register table 2-74 ? output data/enable register propagation delays worst commercial-case conditions: t j = 85c, vdd = 1.14 v parameter description measuring nodes (from, to)* ?1 std. units toclkq clock-to-q of the outp ut/enable register tbd tbd ns tosud data setup time for the output/enable register tbd tbd ns tohd data hold time for the output/enable register tbd tbd ns tosue enable setup time for the output/enable register tbd tbd ns tohe enable hold time for the output/enable register tbd tbd ns tosusl synchronous load setup time for the output/enable register tbd tbd ns tohsl synchronous load hold time for the output/enable register tbd tbd ns toaln2q asynchronous clear-to-q of the output/enable register (adn = 1) tbd tbd ns asynchronous preset-to-q of the output/enable register (adn = 0) tbd tbd ns toremaln asynchronous load removal time for the output/enable register tbd tbd ns torecaln asynchronous load recovery time for the output/enable register tbd tbd ns towaln asynchronous load minimum pulse width for the output/enable register tbd tbd ns tockmpwh clock minimum pulse width high for the output/enable register tbd tbd ns tockmpwl clock minimum pulse width low for the output/enable register tbd tbd ns note: *for the derating values at specific junction temperature and voltage supply levels, refer to table 2-11 on page 2-14 for derating values.
smartfusion2 system-on-chip fpgas revision 0 2-67 advance information (s ubject to change) ddr module specification input ddr module figure 2-2 ? input ddr module sle d en aln adn sln sd lat clk q sle d en aln adn sln sd lat clk q qr qf ddr_in latch d aln adn clk q d en aln adn sln sd lat clk a b c d e f g
smartfusion2 dc and switching characteristics 2-68 revision 0 advance information (s ubject to change) input ddr timing diagram figure 2-3 ? input ddr timing diagram t ddrial2q2 t ddriremal 123456789 clk d aln qf qr 4 6 8 t ddrihd t ddrisud t ddriclkq2 t ddrial2q1 t ddriclkq1 3 5 7 10 11 adn sd t ddrirecal sln t ddrihsln t ddrisusln en 1 t ddrisue t ddrihe t ddriwal t ddrickmpwl t ddrickmpwh
smartfusion2 system-on-chip fpgas revision 0 2-69 advance information (s ubject to change) timing characteristics table 2-75 ? input ddr propagation delays parameter description measuring nodes (from, to) ?1 std. units tddriclkq1 clock-to-out out_qr for input ddr b, c 0.178 0.209 ns tddriclkq2 clock-to-out out_qf for input ddr b, d 0.175 0.205 ns tddrisud data setup for input ddr a, b 0.464 0.546 ns tddrihd data hold for input ddr a, b 0 0 ns tddrisue enable setup for input ddr e, b tbd tbd ns tddrihe enable hold for input ddr e, b 0 0 ns tddrisusln synchronous load setup for input ddr g, b 0.577 0.679 ns tddrihsln synchronous load hold for input ddr g, b 0 0 ns tddrial2q1 asynchronous load-to-out qr for input ddr f, c 0.618 0.727 ns tddrial2q2 asynchronous load-to-out qf for input ddr f, d 0.569 0.67 ns tddriremal asynchronous load removal time for input ddr f, b 0 0 ns tddrirecal asynchronous load recovery ti me for input ddr f, b 0.041 0.048 ns tddriwal asynchronous load minimum pulse width for input ddr f, f 0.32 0.376 ns tddrickmpwh clock minimum pulse width high for input ddr b, b 0.08 0.094 ns tddrickmpwl clock minimum pulse widt h low for input ddr b, b 0.068 0.08 ns
smartfusion2 dc and switching characteristics 2-70 revision 0 advance information (s ubject to change) output ddr module figure 2-4 ? output ddr module sle d en aln adn sln sd lat clk q sle d en aln adn sln sd lat clk q qr qf ddr_ out en aln adn sln sd lat clk 1 q dr df 0 g a b c d e f
smartfusion2 system-on-chip fpgas revision 0 2-71 advance information (s ubject to change) figure 2-5 ? output ddr timing diagram ` 67 2 1 8 3 910 45 28 9 t ddroremal t ddrohdr t ddrosudr t ddrohdf t ddrosudf t ddroclkq t ddrorecal clk df dr aln out t ddroal2q 7 1 4 11 adn sd sln en 10 t ddrosue t ddrohde t ddrosusln t ddrohdsln t ddrockmpwl t ddrockmpwh
smartfusion2 dc and switching characteristics 2-72 revision 0 advance information (s ubject to change) timing characteristics table 2-76 ? output ddr propagation delays parameter description measuring nodes (from, to) ?1 std. units tddroclkq clock-to-out of ddr for output ddr e, g 0.288 0.339 ns tddrosudf data_f data setup for output ddr f, e 0.154 0.181 ns tddrosudr data_r data setup for output ddr a, e tbd tbd ns tddrohdf data_f data hold for output ddr f, e 0 0 ns tddrohdr data_r data hold for output ddr a, e 0 0 ns tddrosue enable setup for input ddr b, e 0.148 0.174 ns tddrohe enable hold for input ddr b, e 0 0 ns tddrosusln synchronous load setup for input ddr d, e 0.79 0.93 ns tddrohsln synchronous load hold for input ddr d, e 0 0 ns tddroal2q asynchronous load-to-out for output ddr c, g 0.575 0.677 ns tddroremal asynchronous load removal time for output ddr c, e 0 0 ns tddrorecal asynchronous load recovery time for output ddr c, e 0.775 0.911 ns tddrowal asynchronous load minimum pulse width for output ddr c, c 0.191 0.224 ns tddrockmpwh clock minimum pulse width high for the output ddr e, e 0.101 0.119 ns tddrockmpwl clock minimum pulse width low for the output ddr e, e 0.156 0.184 ns
smartfusion2 system-on-chip fpgas revision 0 2-73 advance information (s ubject to change) logic module specifications 4-input lut (lut-4) the smartfusion2 offers a fully permutable 4-input lut. in this section, timing characteristics are presented for a sample of the library. timing characteristics figure 2-6 ? lut-4 t pd pad a b y pad pad pad d/s (where applicable) adn4 or any combinational logic pad c t pd t pd t pd t pd (rr) a, b, c, d, s out 50% gnd (ff) 50% 50% 50% vdd vdd gnd (rf) 50% t pd = max(t pd (rr), t pd (rf), t pd (ff), t pd (fr)) where edges are applicable for the particular combinatorial cell (fr) 50% vdd out gnd table 2-77 ? combinatorial cell propagation delays combinatorial cell equation parameter ?1 std. units notes inv y = !a tpd 0.108 0.127 ns and2 y = a b tpd 0.172 0.203 ns nand2 y = !(a b) tpd 0.16 0.188 ns or2 y = a + b tpd 0.172 0.203 ns nor2 y = !(a + b) tpd 0.16 0.188 ns xor2 y = a b tpd 0.172 0.203 ns xor3 y = a b c tpd 0.24 0.283 ns and3 y = a b c tpd 0.22 0.259 ns and4 y = a b c d tpd 0.493 0.58 ns
smartfusion2 dc and switching characteristics 2-74 revision 0 advance information (s ubject to change) sequential module smartfusion2 offers a separate flip flop which can be used independently from the lut. the flip-flop can be configured as a register or a latch and has a data input and optional enable, synchronous load (clear or preset), and asynchronous load (clear or preset). figure 2-8 shows a configuration with sd = 1 (synchronous preset) and adn = 1 (asynchronous clear) for a flip-flop (lat = 0). figure 2-7 ? sequential module sle d en aln adn sln sd lat clk q figure 2-8 ? timing diagram sl aln q clk d e t sue 50% 50% t sud t hd 50% 50% t clkq 1 0 t he t susl t hsl 50% t recaln t remaln t waln t alnq2 t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% sd adn adn = 1 sd = 1 1 50% 0
smartfusion2 system-on-chip fpgas revision 0 2-75 advance information (s ubject to change) timing characteristics table 2-78 ? register delays parameter description ?1 std. units notes tclkq clock-to-q of the core register 0.114 0.134 ns tsud data setup time for t he core register 0.267 0.314 ns thd data hold time for the core register 0 0 ns tsue enable setup time for t he core register 0.353 0.415 ns the enable hold time for the core register 0 0 ns tsusl synchronous load setup time for the core register 0.353 0.415 ns thsl synchronous load hold time for the core register 0 0 ns taln2q asynchronous clear-to-q of the core register (adn = 1) 0.498 0.586 ns asynchronous preset-to-q of the co re register (adn = 0) 0.475 0.559 ns tremaln asynchronous load removal time for the core register 0 0 ns trecaln asynchronous load recovery time for the core register 0.371 0.437 ns twaln asynchronous load minimum pulse width for the core register 0.32 0.376 ns tckmpwh clock minimum pulse width high for the core register 0.079 0.093 ns tckmpwl clock minimum pulse width low for the core register 0.168 0.197 ns
smartfusion2 dc and switching characteristics 2-76 revision 0 advance information (s ubject to change) global resource characteristics smartfusion2 devices offer a powerful, low skew gl obal routing network which provides an effective clock distribution throughout the fpga fabric. refer to the smartfusion2 fpga fabric architecture user?s guide for the positions of various global routing resources. table 2-79 ? m2s050t global resource parameter description speed grade units notes ?1 std. min. max. min. max. trckl input low delay for global clock tbd tbd tbd tbd ns trckh input high delay for global clock tbd tbd tbd tbd ns trckmpwh minimum pulse width high for global clock tbd tbd tbd tbd ns trckmpwl minimum pulse width low for global clock tbd tbd tbd tbd ns trcksw maximum skew for global clock tbd tbd tbd tbd ns
smartfusion2 system-on-chip fpgas revision 0 2-77 advance information (s ubject to change) fpga fabric sram refer to the smartfusion2 fpga fabric architecture user?s guide for more information. fpga fabric large sram (lsram) table 2-80 ? ram1k18 parameter description ?1 std. units min. max. min. max. tcy clock period 1.656 ? 1.948 ? ns tclkmpwh clock minimum pulse width high 0.828 ? 0.974 ? ns tclkmpwl clock minimum pulse width low 0.327 ? 0.384 ? ns tplcy pipelined clock period 1.652 ? 1.944 ? ns tplclkmpwh pipelined clock minimum pulse width high 0.826 ? 0.972 ? ns tplclkmpwl pipelined clock minimum pulse width low 0.324 ? 0.381 ? ns tclk2q read access time with pipeline register ? 0.337 ? 0.396 ns read access time without pipeline register ? tbd ? tbd ns access time with feed-through write timing ? tbd ? tbd ns taddrsu address setup time 0.207 ? 0.244 ? ns taddrhd address hold time 0.041 ? 0.048 ? ns tdsu data setup time 0.33 ? 0.389 ? ns tdhd data hold time 0.074 ? 0.087 ? ns tblksu block select setup time (with pipe-line register enabled) 0.188 ? 0.221 ? ns tblkhd block select hold time (with pipe-lined register enabled) 0.079 ? 0.093 ? ns tblk2q block select to out disable time (when pipe-lined registered is disabled) ? tbd ? tbd ns block select to out enable time (when pipe-lined registered is disabled) ? tbd ? tbd ns tblkmpw block select minimum pulse width tbd ? tbd ? ns trdesu read enable setup time (a_wen, b_wen =0) 0.465 ? 0.547 ? ns trdehd read enable hold time (a_wen, b_wen =0) 0.053 ? 0.063 ? ns trdplesu pipelined read enable setup time (a_dout_en, b_dout_en) 0.703 ? 0.827 ? ns trdplehd pipelined read enable hold time (a_dout_en, b_dout_en) ?0.053 ? ?0.062 ? ns tr2q asynchronous reset to output propagation delay - 0.792 ? 0.931 ns trstrem asynchronous reset removal time tbd ? tbd ? ns trstrec asynchronous reset recovery time 0.005 ? 0.006 ? ns trstmpw asynchronous reset minimum pulse width 0.323 ? 0.38 ? ns tplrstrem pipelined register a synchronous reset removal time tbd ? tbd ? ns tplrstrec pipelined register asyn chronous reset recovery time 0.344 ? 0.405 ? ns tplrstmpw pipelined register asynchronous reset minimum pulse width 0.307 ? 0.361 ? ns tsrstsu synchronous reset setup time 0.231 ? 0.271 ? ns
smartfusion2 dc and switching characteristics 2-78 revision 0 advance information (s ubject to change) fpga fabric micro sram (usram) tsrsthd synchronous reset hold time tbd ? tbd ? ns twesu write enable setup time (a_wen, b_wen = 1) 0.403 ? 0.474 ? ns twehd write enable hold time (a_wen, b_wen = 1) 0.061 ? 0.072 ? ns table 2-80 ? ram1k18 parameter description ?1 std. units min. max. min. max. table 2-81 ? usram (ram64x18) in 64x18 mode parameter description ?1 std. units min. max. min. max. tcy read clock period 0.65 ? 0.766 ? ns tclkmpwh read clock minimum pulse width high 0.296 ? 0.348 ? ns tclkmpwl read clock minimum pulse width low 0.325 ? 0.383 ? ns tplcy read pipe-line clock period 0.622 ? 0.732 ? ns tplclkmpwh read pipe-line clock minimum pulse width high 0.281 ? 0.331 ? ns tplclkmpwl read pipe-line clock minimum pulse width low 0.311 ? 0.366 ? ns tclpl1 minimum pipe-line clock low phas e in order to prevent glitches with pipeline register in latch mode tbd ? tbd ? ns tclk2q read access time with pipeline register ? 0.368 ? 0.433 ns read access time with pipeline register in latch mode ? tbd ? tbd ns read access time without pipeline register ? 1.777 ? 2.09 ns taddrsu read address setup time in synchronous mode 0.172 ? 0.202 ? ns read address setup time in asynchronous mode 1.059 ? 1.246 ? ns taddrhd read address hold time in synchronous mode 0.028 ? 0.033 ? ns read address hold time in asynchronous mode 0.008 ? 0.01 ? ns trdensu read enable setup time 0.245 ? 0.289 ? ns trdenhd read enable hold time 0.074 ? 0.087 ? ns tblksu read block select setup time (with pipe-line register enabled) 0.301 ? 0.355 ? ns tblkhd read block select hold time (with pipe-lined register enabled) tbd ? tbd ? ns tblk2q read block select to out disable time (when pipe-lined registered is disabled) ? 2.093 ? 2.462 ns read block select to out enable time (when pipe-lined registered is disabled) ? 1.503 ? 1.768 ns tblkmpw read block select minimum pulse width tbd ? tbd ? ns trstrem read asynchronous reset removal time (pipelined clock) ?0.002 ? ?0.002 ? ns read asynchronous reset removal time (non-pipelined clock) 0.03 ? 0.036 ? ns
smartfusion2 system-on-chip fpgas revision 0 2-79 advance information (s ubject to change) trstrec read asynchronous reset recovery time (pipelined clock) 0.546 ? 0.642 ? ns read asynchronous reset recovery time (non-pipelined clock) 0.085 ? 0.099 ? ns tr2q read asynchronous reset to output propagation delay (with pipe-line register enabled) ? 0.938 - 1.103 ns read asynchronous reset to output propagation delay (with pipe-line register disabled) ? 1.588 - 1.868 ns tsrstsu read synchronous reset setup time 0.189 ? 0.222 ? ns tsrsthd read synchronous reset hold time 0.074 ? 0.087 ? ns tccy write clock period 1.012 ? 1.192 ? ns tcclkmpwh write clock minimum pulse width high 0.506 ? 0.596 ? ns tcclkmpwl write clock minimum pulse width low 0.297 ? 0.349 ? ns tblkcsu write block se tup time 0.332 ? 0.39 ? ns tblkchd write block hold time tbd ? tbd ? ns tdincsu write input data setup time tbd ? tbd ? ns tdinchd write input data hold time 0.002 ? 0.003 ? ns taddrcsu write address setup time tbd ? tbd ? ns taddrchd write address hold time tbd ? tbd ? ns twecsu write enable setup time 0.32 ? 0.377 ? ns twechd write enable hold time tbd ? tbd ? ns table 2-81 ? usram (ram64x18) in 64x18 mode (continued) parameter description ?1 std. units min. max. min. max.
smartfusion2 dc and switching characteristics 2-80 revision 0 advance information (s ubject to change) on-chip oscillators table 2-82 through table 2-84 on page 2-81 describe the electrical char acteristics of the available on-chip oscillators in smartfusion2 devices. table 2-82 ? electrical characteristics of the crystal oscillator parameter description condition mi n. typ. max. units notes fxtal operating frequency ? 32 ? khz accxtal accuracy temperature: 0c to 85c tbd tbd tbd % cycxtal output duty cycle tbd tbd tbd % jitxtal output jitter period jitter tbd tbd tbd ps rms cycle-to-cyle jitter tbd tbd tbd ps idynxtal operating current tbd tbd tbd ma istbxtal standby current of crystal oscillator tbd tbd tbd a psrrxtal power supply noise tolerance tbd tbd tbd vp-p enxtal enable time tbd tbd tbd s vihxtal input logic level high tbd tbd tbd v vilxtal input logic level low tbd tbd tbd v suxtal startup time test load used: tbd tbd tbd s table 2-83 ? electrical characteri stics of the 25/50 mhz rc oscillator parameter description condition min. typ. max. units notes f25_50rc operating frequency ? 25/50 ? mhz acc25_50rc accuracy temperature: 0c to 85c tbd tbd tbd % cyc25_50rc output duty cycle tbd tbd tbd % jit25_50rc output jitter period jitter tbd tbd tbd ps rms cycle-to-cyle jitter tbd tbd tbd ps idyn25_50rc operating current tbd tbd tbd ma istb25_50rc standby current of crystal oscillator tbd tbd tbd a psrr25_50rc power supply noise tolerance tbd tbd tbd vp-p vih25_50rc input logic level high tbd tbd tbd v vil25_50rc input logic level low tbd tbd tbd v su25_50rc startup time test load used: tbd tbd tbd s
smartfusion2 system-on-chip fpgas revision 0 2-81 advance information (s ubject to change) table 2-84 ? electrical characteristics of the 1 mhz rc oscillator parameter description condition min. typ. max. units notes f1rc operating frequency ? 1 ? mhz acc1rc accuracy temperature: 0c to 85c tbd tbd tbd % cyc1rc output duty cycle tbd tbd tbd % jit1rc output jitter period jitter tbd tbd tbd ps rms cycle-to-cyle jitter tbd tbd tbd ps idyn1rc operating current tbd tbd tbd ma istb1rc standby current of crystal oscillator tbd tbd tbd a psrr1rc power supply noise tolerance tbd tbd tbd vp-p en1rc enable time tbd tbd tbd s vih1rc input logic level high tbd tbd tbd v vil1rc input logic level low tbd tbd tbd v su1rc startup time test load used: tbd tbd tbd s
smartfusion2 dc and switching characteristics 2-82 revision 0 advance information (s ubject to change) clock conditioning circuits (ccc) table 2-85 ? smartfusion2 ccc/ pll specification parameter minimum typical maximum units notes clock conditioning circuitry input frequency f in_ccc 1200mhz clock conditioning circuitry output frequency f out_ccc 20 400 mhz delay increments in programmable delay blocks 100 ps number of programmable values in each programmable delay block 64 acquisition time 500 s tracking jitter tbd ns output duty cycle 48 52 % feedback delay 8ns ccc output peak-to-peak period jitter fccc_out maximum peak-to-peak period jitter sso = 0 0 < sso 2 sso 4 sso 8 sso 16 fg896 fg896 fg896 fg896 fg896 20 mhz to 100 mhz 1 tbd tbd tbd tbd % f out_ccc 100 mhz to 200 mhz 1 tbd tbd tbd tbd % f out_ccc 200 mhz to 400 mhz 1 tbd tbd tbd tbd % f out_ccc spread spectrum characteristics modulation frequency range 25 35 50 khz modulation depth range 0 1.5 % modulation depth control 0.5 %
smartfusion2 system-on-chip fpgas revision 0 2-83 advance information (s ubject to change) serial peripheral interface (spi) characteristics this section describes the dc and switching of th e spi interface. unless otherwise noted, all output characteristics given for a 35 pf load on the pins and all sequential timing characteristics are related to spi_x_clk. for timing parameter definitions, refer to figure 2-9 on page 2-84 . table 2-86 ? spi characteristics commercial case conditions: t j = 85oc, vdd = 1.425 v, ?1 speed grade symbol description and condition m2s050t unit sp1 spi_x_clk minimum period spi_x_clk = pclk/2 ? ns spi_x_clk = pclk/4 tbd ns spi_x_clk = pclk/8 tbd ns spi_x_clk = pclk/16 tbd s spi_x_clk = pclk/32 tbd s spi_x_clk = pclk/64 tbd s spi_x_clk = pclk/128 tbd s spi_x_clk = pclk/256 tbd s sp2 spi_x_clk minimum pulse width high spi_x_clk = pclk/2 ? ns spi_x_clk = pclk/4 tbd ns spi_x_clk = pclk/8 tbd ns spi_x_clk = pclk/16 tbd s spi_x_clk = pclk/32 tbd s spi_x_clk = pclk/64 tbd s spi_x_clk = pclk/128 tbd s spi_x_clk = pclk/256 tbd us sp3 spi_x_clk minimum pulse width low spi_x_clk = pclk/2 ? ns spi_x_clk = pclk/4 tbd ns spi_x_clk = pclk/8 tbd ns spi_x_clk = pclk/16 tbd s spi_x_clk = pclk/32 tbd s spi_x_clk = pclk/64 tbd s spi_x_clk = pclk/128 tbd s spi_x_clk = pclk/256 tbd s sp4 spi_x_clk, spi_x_do, spi_x_ss rise time (10%-90%) tbd ns sp5 spi_x_clk, spi_x_do, spi_x_ss fall time (10%-90%) tbd ns sp6 data from master (spi_x_d o) setup time tbd pclk cycles sp7 data from master (spi_x_d o) hold time tbd pclk cycles sp8 spi_x_di setup time tbd pclk cycles sp9 spi_x_di hold time tbd pclk cycles
smartfusion2 dc and switching characteristics 2-84 revision 0 advance information (s ubject to change) figure 2-9 ? spi timing for a single frame tran sfer in motorola mode (sph = 1) spi_x_clk spo = 0 spi_x_do sp6 sp7 50% 50% msb 50% 50% 50% sp2 sp1 90% 10% 10% sp4 sp5 sp8 sp9 50% 50% msb spi_x_di 10% 90% sp5 90% 10% sp4 90% 10% 10% sp4 sp5 90% spi_x_ss spi_x_clk spo = 1 sp3
smartfusion2 system-on-chip fpgas revision 0 2-85 advance information (s ubject to change) inter-integrated circuit (i 2 c) characteristics this section describes the dc and switching of the i 2 c interface. unless otherwise noted, all output characteristics given are for a 100 pf load on the pins. for timing parameter definitions, refer to figure 2- 10 on page 2-86 . table 2-87 ? i 2 c characteristics commercial case conditions: t j = 85oc, vdd = 1.14 v, ?1 speed grade parameter definition condition value unit vil minimum input low voltage ? see table 2-18 on page 2-22 ? maximum input low voltage ? see ta b l e 2 - 1 8 ? vih minimum input high voltage ? see ta b l e 2 - 1 8 ? maximum input high voltage ? see ta b l e 2 - 1 8 ? vol maximum output voltage low iol = tbd see ta b l e 2 - 1 8 ? iil input current high ? see ta b l e 2 - 1 8 ? iih input current low ? see ta b l e 2 - 1 8 ? vhyst hysteresis of schmitt trigger inputs ?see table 2-17 on page 2-21 v t fall fall time vihmin to vilmax, cload = 400 pf tbd ns vihmin to vilmax, cload = 100 pf tbd ns t rise rise time vilmax to vihmin, cload = 400 pf tbd ns vilmax to vihmin, cload = 100 pf tbd ns cin pin capacitance vin = 0, f = 1.0 mhz tbd pf r pull-up output buffer maximum pull- down resistance ?tbd r pull-down output buffer maximum pull-up resistance ?tbd d max maximum data rate fast mode tbd kbps t low low period of i2c_x_scl ? tbd pclk cycles t high high period of i2c_x_scl ? tbd pclk cycles t hd;sta start hold time ? tbd pclk cycles t su;sta start setup time ? tbd pclk cycles t hd;dat data hold time ? tbd pclk cycles t su;dat data setup time ? tbd pclk cycles t su;sto stop setup time ? tbd pclk cycles t filt maximum spike width filtered ? tbd ns
smartfusion2 dc and switching characteristics 2-86 revision 0 advance information (s ubject to change) figure 2-10 ? i2c timing parameter definition scl t rise t fall t low t hd;sta sda t high t hd;dat t su;dat t su;sto t su;sta s p
revision 0 3-1 3 ? smartfusion2 development tools system designers can leverage the newly released, easy-to-use libero ? system-on-chip (soc) software toolset for designing smartfusion2 devices. libero soc highlights include the following: ? system builder for creation of system level architecture ? synthesis, debug and dsp support from synopsys ? simulation from mentor graphics ? push-button design flow with power analysis and timing analysis ? smartdebug for access to non-invasive probes within smartfusion2 devices ? integrated firmware flows for gnu, iar, and keil ? operating system support includes uclinux from emcraft systems, freertos,? safertos, ? and uc/os-iii? from micrium. libero soc libero soc and libero integrated design environment (ide) are comprehensive software toolsets for designing with microsemi fpgas. different vers ions of libero support different families. ? libero soc v11.0 beta software release suppor ts only the recently announced smartfusion2 soc fpgas. this version includes a new system buil der design approach, spec ifically targeted for smartfusion2 devices. a production version of this software will be available in april 2013, when it will integrate support for the other production flash families cu rrently supported by libero v10.1. ? libero soc v10.1 software release for desig ning with microsemi' s smartfusion, igloo, ? proasic ? 3, and fusion ? families, managing the entire design flow from design entry, synthesis and simulation, through place-and-route, timing and power analysis, with enhanced integration of the embedded design flow. ? libero ide software release for designing wit h microsemi antifuse and legacy flash fpgas and managing the entire design flow from design entry , synthesis and simulation, through place-and- route, timing and power analysis (refer to pcn 1108 ). libero soc introduces a new soc design flow, specific ally targeted to simplify the design of our newest flash fpgas. standalone tools such as silicon scul ptor, flashpro, identify me, and synphony model compiler me are not changing and will continue to include support for all silicon devices. current licenses are valid for both soc and ide releases; a new license is not required for libero soc. figure 3-1 ? tool flow
smartfusion2 development tools 3-2 revision 0 from design, synthesis and simulation, through floo rplanning, place-and-route, timing constraints and analysis, power analysis, and program file generation, libero manages the entire design flow quickly and efficiently. smartdesign provides an efficient methodology for creating complete simple and complex embedded processor-based system-on- chip (soc) designs with ease. the soc design flow provides the designer the choice of using the powerful microprocessor subsystem (mss) standalone or creating a more complex system by utilizing available programmable gates in the fpga fabric. libero enables the designer to conf igure the hardwired cortex-m3 processor, analog (smartfusion only), and peripherals within mss, plus extend additional logic functionality into the fpga fabric, thus taking full advantage of the specific soc fpga device resources. libero provides full power optimization and analysis tools for microsemi's low-power flash fpga families. libero software features libero software offers the latest and best-in-class fpga development tools from leading eda vendors such as mentor graphics and synopsys. these t ools, combined with tools developed by microsemi, allow you to quickly and easily manage your microsem i fpga designs. an intuitive user interface and powerful design manager guide you through the process while organizing design files and seamlessly managing exchanges between the various tools. ? powerful project and design flow management ? full suite of integrated design entry tools and methodologies: ? smartdesign graphical soc design creation with automatic abstraction to hdl ? core catalog and configuration ? fabric utilization for smartfusion2 designs ? hdl and hdl templates ? user-defined block creation flow for design re-use ? microsemi cell libraries ? synplify pro ? me synthesis fully optimizes microsemi fpga device performance and area utilization ? synphony model compiler me performs high-lev el synthesis optimizations within a simulink ? environment ? modelsim ? me vhdl or verilog behavioral, post-synt hesis and post-layout simulation capability ? designer physical design implementation, floorplanning, physical constraints, and layout ? timing-driven and power-driven place-and-route ? smarttime environment for timing constraint management and analysis ? smartpower provides comprehensive power analysis for actual and "what if" power scenarios ? interface to flashpro programmers ? post-route probe insertion and identify ? ae debugging software for microsemi flash designs ? supported on microsoft ? windows ? and redhat linux operating systems system builder system builder ( figure 3-2 on page 3-3 ) is a new graphical design wizard designed specifically for smartfusion2 based designs. system builder wa lks the user through the following steps: ? asks the user basic questi ons on system architecture ? adds any additional peripherals in the fabric ? walks through configuration options for each selected feature ? builds complete base system and api ? correct by design
smartfusion2 system-on-chip fpgas revision 0 3-3 smartdebug smartdebug is a new debug tool added in libero soc v11.0 software that supports probe capabilities in the smartfusion2 architecture and also supports device debug features for memory. smartfusion2 devices have built-in probe points that greatly enhance the ability to debug logic elements within the device. the enhanced debug featur es implemented in smartfusion2 devices give access to any logic element and enable designers to check the state of inputs and outputs in real time. live probe and active probe are only available on the smartfusion2 family of products. ? with live probe, two dedicated probes can be configured to observe a probe point which is any input or output of a logic elem ent. the probe data can then be sent to an oscilloscope or even redirected back to the fpga fabric to drive a software logic analyzer. ? active probe allows dynamic asynchronous read and write to a flip-flop or probe point. this enables a user to quickly observe the output of t he logic internally or to quickly experiment on how the logic will be affected by writing to a probe point. ? memory debug gives the ability to perform dynamic asynchronous reads and writes to a micro sram or large sram block so the user can quickly verify if the content of the memory is changing as expected. smartdebug features can be accessed from within the libero design flow or flashpro software. figure 3-2 ? system builder
smartfusion2 development tools 3-4 revision 0 softconsole microsemi's embedded softwa re development environment softconsole is microsemi's free software developm ent environment that enables the rapid production of c and c++ executables for microsemi fpgas usin g cortex-m3, cortex-m1, and core8051s. libero soc automatically generates softconsole projects and firmware for soc fpga designs. softconsole includes a fully integrated debugger that offers easy a ccess to memory contents, registers, and single- instruction execution. product features softconsole ( figure 3-3 on page 3-5 ) provides a flexible and easy-to-use graphical user interface for managing your embedded software development projects. you can quickly develop and debug software programs and implement them in microsemi fpgas. softconsole e nables you to configure project settings, edit and debug software programs, and organize your files. with this tool you have simultaneous access to multiple tool windows and the ability to quickly switch editing and debug views. ? available for free download ? eclipse-based ide ? gnu c/c++ compiler (cortex-m3 and cortex-m1) ? sdcc compiler (core8051s) ? gdb debugger ? flashpro4/3/3x compatible debug sprite ? seamless access to and debug of flash memory (smartfusion2 envm, fusion nvm, external flash) ? simultaneous access to multiple tool windows ? fast switch between c/c++ and debug ? one or more perspectives in a workbench window ? perspectives can be customized by the user ? provides a direct interface to: ? smartfusion2 microcontroller subsyst em (mss) for smartfusion2 designs ? firmware catalog, which includes cmsis-pal for cortex-m3, hals fo r cortex-m1 and 8051s, driver firmware packages, sample programs, and linker scripts ? compatible with libero soc and ide design flows
smartfusion2 system-on-chip fpgas revision 0 3-5 softconsole user interface figure 3-3 ? softconsole user interface
smartfusion2 development tools 3-6 revision 0 firmware catalog the firmware catalog is a standalone executable progr am that supports microsemi softconsole, keil?, and iar systems ? embedded processor development toolch ains targeting the arm cortex-m3, cortex-m1, and core8051s processors. the firmware catalog streamlines locating and generating firmware that is compatible with intellectual property (ip) cores used in microsemi fpga designs. firmware can also be delivered through smartdesign within the libero environment. software drivers microsemi has a broad offering of proven and pre-im plemented synthesizable ip building blocks that can be easily configured and used within microsemi fpga system-level designs. software drivers for many microsemi ip cores are available within the firmware catalog. the drivers are free of charge and delivered as c source, so they can be easily comp iled and linked into a user's program or executable. these drivers hide the implementat ion details of peripheral operations behind a driver application program interface (api), so the developer need only be concerned with the peripheral's function. hardware abstraction layers a hardware abstraction layer (hal) that supports arm cortex-m3, cortex-m1 and core8051s processors is also available. hals enable the softwa re driver to be used without modification, isolating the driver's implementation from the hardware platfo rm variations. a driver implementation interacts with the hardware peripheral it is controlling. this enables programmers to seamlessly reuse code, even when the hardware platform changes. the firmware catalog notifies the user if new firm ware cores or firmware updates are available from microsemi's web repository. the updat es can be downloaded into a local vault on a pc. a vault is a local directory (either local to a machine or on the local network) that contains cores downloaded from one or more repositories. the repository is a location on t he web that contains firmware cores ready to be used directly in any toolchain software. figure 3-4 ? hardware abstraction layer vault (local or remote) firmware catalog softconsole web repositories (microsemi, other) browse for firmware access repositories load program download generate core
smartfusion2 system-on-chip fpgas revision 0 3-7 after selecting ips to use in the microsemi fpga des ign, the associated firmware can be selected in the firmware catalog and the ip cores can be generated. the ip cores are then loaded into the code via softconsole, keil, or iar systems software development environments. for the soc design flow, the designer does not need to determine which firmware must be selected and generated. although the desi gner can browse the complete listing of firmware in the firmware catalog, the smartdesign flow for smartfusion2 and smartfus ion searches the design for instantiated ip and automatically presents th e appropriate firmware. firmware catalog user interface the firmware catalog is configured within softconsole so that it is integrated in the toolchain, which allows seamless location, configuration, and additi on of firmware to the user's softconsole project. figure 3-5 ? firmware catalog user interface
smartfusion2 development tools 3-8 revision 0 soc fpga ecosystem microsemi has a long history of supplying compre hensive fpga development tools and recognizes the benefit of partnering with i ndustry leaders to deliver the optimum us ability and productivity to customers. taking the same approach with processor developm ent, microsemi has partnered with key industry leaders in the microcontroll er space to provide the r obust soc fpga ecosystem. microsemi is partnering with keil and iar to provide software id e support to system designers. the result is a robust solution that can be easily adopted by developers who are already doing embedded design. the learning path is st raightforward for fpga designers. figure 3-6 shows a software stack with examples of driv ers, rtos and middleware from microsemi and partners. by leveraging the software stack, designers can decide at which level to add their own customization to their design, thus speeding ti me to market and reducing overhead in the design. figure 3-6 ? software stack customer secret sauce tcp/ip, http, smtp, dhcp, lcd c/os-iii, rtx, uclinux, freertos application layer middleware os/rtos drivers hardware abstraction layer hardware platform microsemi cmsis-based hal microsemi smartfusion2 i2c spi uart can usb ethernet timer envm ...
smartfusion2 system-on-chip fpgas revision 0 3-9 arm because an arm processor was chosen for smartfusion2 and smartfusion devices, microsemi's customers can benefit from the extensive arm ec osystem. by building on mi crosemi supplied hardware abstraction layer (hal) and drivers, third party vendo rs can easily port rtos and middleware for the smartfusion devices. ? arm cortex-m series processors ? arm cortex-m3 processor resources ? arm cortex-m3 technical reference manual ? arm cortex-m3 processor software develo pment for arm7tdmi processor programmers white paper compile and debug microsemi's softconsole is a free eclipse-based id e that enables the rapid production of c and c++ executables for microsemi fpgas and csocs using cortex-m3, cortex-m1, and core8051s. for smartfusion support, softconsole includes the gnu c/c++ compiler and gdb debugger. additional examples can be found on the softconsole page. using uart with smartfusion csoc: softconsole standalone flow tutorial displaying pot level with leds: libero soc and so ftconsole flow tutorial for a smartfusion csoc iar embedded workbench ? for arm/cortex is an integrated development environment for building and debugging embedded arm applications using assembler, c and c++. it includes a project manager, editor, build and debugger tools with support for rtos -aware debugging on hardware or in a simulator. ? designing smartfusion with iar systems ? iar embedded workbench for arm keil's microcontroller development kit comes in two editions: mdk-arm and mdk basic. both editions feature vision ? , the arm compiler, microlib, and rtx, but th e mdk basic edition is limited to 256k so that small applications are more affordable. ? designing smartfusion with keil ? using keil vision and microsemi smartfusion ? keil microcontroller development kit for arm product manuals ? download evaluation version of keil mdk-arm software ide softconsole keil mdk iar embedded workbench ? website www.microsemi.com/soc www.keil.com www.iar.com free versions from soc products group free with libero soc 32 k code limited 32 k code limited available from vendor n/a full version full version compiler gnu gcc realview c/c++ iar arm compiler debugger gdb debug vision debugger c-spy ? debugger instruction set simulator no vision simulator yes debug hardware flashpro4 ulink2 ? or ulink-me j-link? or j-link lite
smartfusion2 development tools 3-10 revision 0 operating systems freertos? is a portable, open source, royalty free, mi ni real-time kernel (a free-to-download and free- to-deploy rtos that can be used in commercial applications without any re quirement to expose your proprietary source code). freertos is scalable and designed specifically for small embedded systems. this freertos version ported by mi crosemi is 6.0.1. for more inform ation, visit the freertos website: www.freertos.org ? smartfusion webserver demo using uip and freertos ? smartfusion: running webserver, tftp on iwip tcp/ip stack application note emcraft systems provides porting of the open -source u-boot firmware and uclinux? kernel to smartfusion, a linux-based cro ss-development framework, and other complementary components. combined with the release of its a2f-linux evaluation kit , this provides a low-cost platform for evaluation and development of linux (uclinux) on th e cortex-m3 cpu core of microsemi smartfusion2 devices. ? emcraft linux on microsemi's smartfusion keil offers the rtx real-time kernel as a roya lty-free, deterministic rtos designed for arm and cortex-m devices. it allows you to create programs that simultaneously perfo rm multiple functions and helps to create applications wh ich are better structured and more easily maintained. ? the rtx real-time kernel is included with mdk-arm. download the evaluation version of keil mdk-ar . ? rtx source code is available as part of keil/a rm real-time library (rl-arm), a group of tightly- coupled libraries designed to solve the real-time and communication challenges of embedded systems based on arm-powered microcontroller devices. the rl-arm library now supports smartfusion devices and designers with additional key features listed in the "middleware" section on page 3-11 . micrium supports smartfusion with the company's fl agship c/os family, recognized for a variety of features and benefits, including unparalleled re liability, performance, depe ndability, impeccable source code and vast documentation. micrium supports th e following products for smartfusion devices and continues to work with microsemi on additional projects. ? c/os-iii, micrium's newest rtos, is designed to save time on your next embedded project and puts greater control of the software in your hands. ? smartfusion quickstart guide for micrium c/os-iii examples rowebots provides an ultra tiny linux-compatible rtos called unison for smartfusion. unison consists of a set of modular software components, which, lik e linux, are either free or commercially licensed. unison offers posix ? and linux compatibility with hard real-tim e performance, complete i/o modules and an easily understood environment for device dr iver programming. seamless integration with fpga and analog features are fast and easy. ? unison v4-based products include a free unison v4 linux and posix-compatible kernel with serial i/o, file system, six dem onstration programs, upgraded doc umentation and source code for unison v4, and free (for non-commercial use) unison v4 tcp/ip server. commercial license upgrade is available for unison v4 tcp/ip se rver with three dem onstration programs, dhcp client and source code. ? unison v5-based products include commercial un ison v5 linux- and posix-compatible kernel with serial i/o, file system, extensive feature set, full documentation, source code and more than 20 demonstration programs, unis on v5 tcp/ipv4 with extended fe ature set, sockets interface, multiple network interfaces, ppp support, dhcp client, docum entation, source code and six demonstration programs, and multiple other features.
smartfusion2 system-on-chip fpgas revision 0 3-11 middleware microsemi has ported both uip and iwip for ethernet support as well as including tftp file service. ? smartfusion webserver demo using uip and freertos ? smartfusion: running webserver, tftp on iwip tcp/ip stack application note the keil/arm real-time library (rl-arm)* in addition to rtx source includes: ? rl-tcpnet (tcp/ip) ? the keil rl-tcpnet library, supporting full tcp/ip an d udp protocols, is a full networking suite specific ally written for small arm and cortex-m processor-based microcontrollers. tcpnet is now ported to and supports smartfusion cortex-m3. it is highly optimized, has a small code footpr int, and gives excellent performance, providing a wide range of application level protocols and examples such as ftp, snmp, soap, and ajax. an http server example of tcpnet working in a smartfusion design is available. ? the flash file system (rl-flash) allows your embedded applications to create, save, read, and modify files in standard storage devices such as rom, ram, or flashrom, using a standard serial peripheral interface (spi). many arm-bas ed microcontrollers have a practical requirement for a standard file system. with rl-flashfs you can implement new features in embedded applications such as data logging, storing program state during standby modes, or storing firmware upgrades. note: * the can and usb functions within rl-a rm are not supported for smartfusion. micrium in addition to their c/os-iii of fers the following support for smartfusion: ? c/tcp-ip? is a compact, reliable and high -performance stack built from the ground up by micrium and has the quality, scalability and reliabi lity that translates into a rapid configuration of network options, remarkable ease-of-use and rapid time-to-market. ? c/probe? is one of the most useful tools in embedded system s design and puts you in the driver's seat, allowing you to take charge of virt ually any variable, memory location, and i/o port in your embedded product, while your system is running.
smartfusion2 development tools 3-12 revision 0 smartfusion2 development kit the smartfusion2 development kit allows access to the peripherals of the smartfusion2 soc fpga. this board is designed to support full application de velopment and prototyping. the kit will also serve as a motherboard for several application-specific d aughtercards that will be rolled over the next year. ? motor control interface card supports up to 6 motor daughtercards ? system management daughtercard ? aviation daughtercard figure 3-7 ? smartfusion2 development kit figure 3-8 ? smartfusion2 applications
revision 0 4-1 4 ? pin descriptions smartfusion2 devices support multi-standard i/os (msio), microcontroller serial interfaces, high speed serial interfaces, and a debugging jtag interface. smartfusion2 devices require all the power supplies listed in ta b l e 4 - 1 . supply pins table 4-1 ? supply pins name type description min. (v) max. (v) vss ground ground pad for core and i/os pll0_vssa ground vdda to on-die vssa high pass filter connection for pll0. if unused, it must be grounded. pll0_vdda supply analog power pad for pll0 2.5 3.3 pll1_vssa ground vdda to on-die vssa high pass filter connection for pll1. if unused, it must be grounded. pll1_vdda supply analog power pad for pll1 2.5 3.3 pll2_vssa ground vdda to on-die vssa high pass filter connection for pll2. if unused, it must be grounded. pll2_vdda supply analog power pad for pll2 2.5 3.3 pll3_vssa ground vdda to on-die vssa high pass filter connection for pll3. if unused, it must be grounded. pll3_vdda supply analog power pad for pll3 2.5 3.3 pll4_vssa ground vdda to on-die vssa high pass filter connection for pll4. if unused, it must be grounded. pll4_vdda supply analog power pad for pll4 2.5 3.3 pll5_vssa ground vdda to on-die vssa high pass filter connection for pll5. if unused, it must be grounded. pll5_vdda supply analog power pad for pll5 2.5 3.3 pll_pcie_0_vssa ground vdda to on-die vssa high pass filter connection for pll pcie0. if unused, it must be grounded. pll_pcie_0_vdda supply high supply voltage for pll pcie0. if unused, should be connected to +3.3 v. 2.5 3.3 pll_pcie_1_vssa ground vdda to on-die vssa high pass filter connection for pll pcie1. if unused, it must be grounded pll_pcie_1_vdda supply high supply voltage for pll pcie1. if unused, should be connected to +3.3 v. 2.5 3.3 notes: 1. pcie0 for serdesif_0 an d pcie1 for serdesif_1 2. vref is not used in differential mode. 3. the m2s050t device has two serdesi fs (serdesif_0, serdesif_1), which reside on 2 i/o banks (bank 6 and bank 9) out of a total of 10 i/o banks.
pin descriptions 4-2 revision 0 pcie0vdd supply pcie/pcs supply. if unused, should be connected to +1.2 v. 11.2 pcie0vddiol 1 supply tx/rx analog i/o voltage. low voltage power for pcie0 for lane0 and lane1 of serdesif_0, located on the left side. if unused, should be connected to +1.2 v. 1.2 1.2 pcie0vddior 1 supply tx/rx analog i/o voltage. low voltage power for pcie0 for lane2 and lane3 of serdesif_0, located on the right side. if unused, should be connected to +1.2 v. 1.2 1.2 pcie0pllrefretl 1 local on-chip ground return path for pcie0vddplll for lane0 and lane1 of serdesif_0, located on the left side. do not short to gnd on the package or pcb. for details, refer to the "high speed board design guidelines?- serdes i/os section. if unused, it can be left floating. pcie0vddplll 1 supply analog power for se rdes pll of pcie0 lanes 0&1. if unused, should be connected to +2.5 v 2.5 2.5 pcie0pllrefretr 1 local on-chip ground return path for pcie0vddpllr for lanes 2 and 3 of serdesif_0 that is located on right side. do not short to gnd on the package or pcb. if unused, it can be left floating. pcie0vddpllr 1 supply analog power for serdes pll of pcie0 lane2 and lane3. if unused, should be connected to +2.5 v. 2.5 2.5 pcie1vdd supply pcie/pcs supply. if unused, should be connected to +1.2 v. 11.2 pcie1vddiol 1 supply tx/rx analog i/o voltage. low voltage power for pcie1 for lane0 and lane1 of serdesif_1, located on the left side. if unused, should be connected to+1.2 v. 1.2 1.2 pcie1vddior 1 supply tx/rx analog i/o voltage. low voltage power for pcie1 for lane2 and lane3 of serdesif_1, located on the right side. if unused, should be connected to +1.2 v. 1.2 1.2 pcie1pllrefretl 1 local on-chip ground return path for pcie1vddplll for lane0 and lane1 of serdesif_1, located on left side. do not short to gnd on the package or pcb. if unused, it can be left floating. pcie1vddplll 1 supply analog power for serdes pll of pcie1 lane0 and lane1. if unused, connect to +2.5 v. 2.5 2.5 table 4-1 ? supply pins (continued) name type description min. (v) max. (v) notes: 1. pcie0 for serdesif_0 an d pcie1 for serdesif_1 2. vref is not used in differential mode. 3. the m2s050t device has two serdesi fs (serdesif_0, serdesif_1), which reside on 2 i/o banks (bank 6 and bank 9) out of a total of 10 i/o banks.
smartfusion2 system-on-chip fpgas revision 0 4-3 pcie1pllrefretr 1 local on-chip ground return path for pcie1vddpllr for lane2 and lane3 of serdesif_1, located on right side. do not short to gnd on the package or pcb. if unused, it can be left floating. pcie1vddpllr 1 supply analog power for serdes pll of pcie1 lane2 and lane3. if unused, should be connected to +2.5 v. 2.5 2.5 pll_mddr_vssa ground analog gr ound pad for pll mddr pll_mddr_vdda supply analog power pad for pll mddr 2.5 3.3 pll_fddr_vssa ground analog gr ound pad for pll of fddr pll_fddr_vdda supply analog power pad for pll of fddr 2.5 3.3 vref0 2 supply reference voltage for fddr (bank 0) 0.50 * vddi0 0.50 * vddi0 vref5 2 supply reference voltage for mddr (bank 5) 0.50 * vddi5 0.50 * vddi5 vssnvm ground envm ground vppnvm supply envm power pad 2.5 3.3 vddi0 supply vddi port 0, bank 0 power 1.2 2.5 vddi1 supply vddi port 1, bank 1 power 1.2 3.3 vddi2 supply vddi port 2, bank 2 power 1.2 3.3 vddi3 supply vddi port 3, bank 3 power 1.2 3.3 vddi4 supply vddi port 4, bank 4 power 1.2 3.3 vddi5 supply vddi port 5, bank 5 power 1.2 2.5 vddi6 supply vddi port 6, bank 6 power 1.2 2.5 vddi7 supply vddi port 7, bank 7 power 1.2 2.5 vddi8 supply vddi port 8, bank 8 power 1.2 3.3 vddi9 supply vddi port 9, bank 9 power 1.2 2.5 vdd supply low voltage supply port 1 1.2 vpp supply power for charge pumps 2.5 3.3 table 4-1 ? supply pins (continued) name type description min. (v) max. (v) notes: 1. pcie0 for serdesif_0 an d pcie1 for serdesif_1 2. vref is not used in differential mode. 3. the m2s050t device has two serdesi fs (serdesif_0, serdesif_1), which reside on 2 i/o banks (bank 6 and bank 9) out of a total of 10 i/o banks.
pin descriptions 4-4 revision 0 dedicated global i/o naming conventions dedicated global i/os are dual-use i/os which can driv e the global blocks either directly or through clock conditioning circuits (ccc) or virtual clock conditi oning circuits (vccc). they can also be used as regular i/os. these global i/os are the primary source for bringing in the external clock inputs into the smartfusion2 device. in the m2s050t device, there are 16 global blo cks located in the center of the fabric and 32 global i/os located 8 each on the north, east, south, and west sides of the fabric. there are 6 ccc blocks, located 2 ea ch on northwest, northeas t, and southwest side of the fabric and 2 vccc blocks on the southeas t side of the fabric. dedicated global i/os that drive the global blocks (gb) directly are named as gbn, where n is 0 to 15. dedicated global i/os that drive gbs through cccs are named as ccc_xyz_lw , where: xy is the location?ne, sw, or nw. z is 0 or 1. i represents i/o w refers to one of the four possible output clocks of the asso ciated ccc_xyz?gl0, gl1, gl2, or gl3. dedicated global i/os that drive gbs through vcccs are named as vccc_sez , where: se is southeast. z is 0 or 1. unused global pins are configured as inputs with pull-up resistors by libero software. for further details, refer to the "fabric gl obal routing resources" chapter of the smartfusion2 fpga fabric architecture user?s guide . user i/o naming conventions the naming convention used for each fpga user i/o is ioxybz, where: io is the type of i/o?msio, msiod, or ddrio for the m2s050t device: msio x is the i/o pair number in bank z , starting at 0 from bank 3 (southeast) and proceeding in a counter-clockwise direction to bank 2 and bank 1. msiod x is the i/o pair number in bank z, starting at 93 from bank9 (northwest) and proceeding in a counter-clockwise direction to bank7 and bank6. ddrio x is the i/o pair number in bank z, starting at 49 from bank0 (north) to bank5 (south). y is p (positive) or n (negative). in single-ended mode, the i/o pair operates as two separate i/os named p and n. differential mode is implemented wi th a fixed i/o pair and cannot be split with an adjacent i/o. b is bank. z is the bank number?0 to 9. differential standards are implemented as true di fferential outputs and complementary single-ended outputs for sstl/hstl. in the single-ended mode, the i/o pair operates as two separate i/os named p and n. all the configuration and data inputs/outputs are then separate and use names ending in p and n to differentiate between the two i/os. for more information, refer to the "i/os" chapter of the smartfusion2 fpga fabric architecture user?s guide .
smartfusion2 system-on-chip fpgas revision 0 4-5 multi-standard i/o smartfusion2 devices feature a flexible i/o structure that supports a range of mixed voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v) through bank selectio n. the msio, msiod, and ddrio can be configured as differential i/os or two single-ended i/os. th ese i/os use one i/o slot to implement single-ended standards and two i/o slots for differential standar ds. the ddrio is shared between fabric logic and mddr/fddr whereas msio/msiod is shared between mss peripherals and fabric logic. when you do not use an mddr/fddr controller or ms s peripherals, the respective i/os are available to fabric logic. for functional block diagrams of ms io, msiod, and ddrio, refer to the smartfusion2 fpga fabric architecture user?s guide . for supported i/o standards, refer to the supported voltage standards table in the smartfusion2 fpga fabric architecture user?s guide . figure 4-1 ? smartfusion2 (m2s050t) i/o bank location and naming smartfusion2 soc fpga bank 8 msio (23 pairs) bank 7 msiod (27 pairs) bank 6 msiod/serdes_0 (2 pairs) bank 9 msiod/serdes_1 (2 pairs) bank 2 msio (13 pairs) bank 3 msio (25 pairs) bank 4 msiod/jtag (3 pairs) bank 1 msio (11 pairs) bank 0 ddrio (mddr) (44 pairs) bank 5 ddrio (fddr) (44 pairs)
pin descriptions 4-6 revision 0 i/o programmable features smartfusion2 devices support different i/o programm able features for msio, msiod, and ddrio. each i/o pair (p, n) supports the following programmable features: ? programmable drive strength ? programmable weak pull-up and pull-down ? configurable odt and driver impedance ? programmable input delay ? programmable schmitt input and receiver for more information on smartfusion2 i/o programmable features, refer to the smartfusion2 i/o feature table of the smartfusion2 fpga fabric architecture user's guide . table 4-2 ? multi-standard i/o types name type description msioxybz in/out msios provide programm able drive strength, weak pull-up, and weak-pull-down. in single- ended mode, the i/o pair operates as two separa te i/os named p and n. some of these pins are also multiplexed with integr ated peripherals in the mss (i2c, usb, spi, uart, can, and fabric i/os).this allows msio pins to be mu ltiplexed as i/os for t he fpga fabric, the arm cortex-m3 processor, or for given integr ated mss peripherals. msios can be routed to dedicated i/o buffers (mssiobuf) or in some cases to the fpga fabric interface through an iomux. smartfusion2 i/o ports also support esd protection. msiodxybz in/out msiod is very similar to msio, but dr ops 3.3 v and hot-plug suppo rt and adds pre-emphasis, in order to achieve higher speeds. msiods provide programmable drive strength, weak pull-up, and weak pull-down. msiod i/o cells operate at up to 2.5 v and are capable of high-speed lvds operation. some of these pins are also multiplexed with the serdes interface. smartfusion2 i/o ports support esd protection. ddrioxybz in/out the double data i nput output (ddrio) is a multi-standard i/o optimized for lpddr/ddr2/ddr3 performance. in smartfus ion2 devices there are two ddr subsystems: the fabric ddr and mss ddr controllers. all ddrios can be configured as differential i/os or two single-ended i/os. if you select m ddr/fddr, libero soc automatically connects mddr/fddr signals to the ddrios. ddrios can be connected to the respective ddr subsystem phys or can be used as user i/os. depending on the memory configuration, only the required ddrios are used by libero soc. the unused ddrios are available to connect to the fabric.
smartfusion2 system-on-chip fpgas revision 0 4-7 impedance calibration there are two ddrio calibration blocks in each smartfusion2 m2s050t device. the mddr and fddr have a ddrio calibration block. the ddrio can use fixed impedance calibration for different drive strengths, and these values can be programmed using libero soc for the selected i/o standard. these values are fed to the pull-up/pull-down referenc e network to match the impedance with an external resistor. for the different drive modes, refer to the smartfusion2 fpga fabric ar chitecture user?s guide for reference resistor values. dedicated i/os dedicated i/os ( table 4-4 and table 4-6 on page 4-8 ) can be used for a single purpose such as serdes, device reset, or clock functions. smartfusion2 dedicated i/os: ? device reset i/os ? crystal oscillator i/os ? serdes i/os table 4-3 ? reference resistors pin name reference resistor (ohm) fddr_imp_calib_ecc pulled down with 240, 150, 300, or 191 ohms, depending on voltage/standard desired for optimization. mddr_imp_calib_ecc pulled down with 240, 150, 300, or 191 ohms, depending on voltage/standard desired for optimization. table 4-4 ? device reset and crystal oscillator pin types and descriptions pin type i/o description device reset i/os devrst_n analog input device reset; asserted low and powered by vpp crystal oscillator i/os extlosc analog input crystal connection or external rc network. xtlosc analog input input clock from the main crystal oscillator table 4-5 ? programming spi interface name type description sc_spi_ss out spi slave select sc_spi_sdo out spi data output sc_spi_sdi in spi data input sc_spi_clk out spi clock flash_golden in if pulled high, this indicates that the device is to be re-programmed from an image in the external spi flash attached to the spi interface. if pulled low, the spi is put into slave mode.
pin descriptions 4-8 revision 0 serdes i/os the serdes i/os available in smartfusion2 devices are dedicated for high speed serial communication protocols. the serdes i/os support protocols such as pci express 2.0, xaui, serial gigabit media independent interface (sgmii), serial rapid io (srio) , and any user-defined high speed serial protocol implementation in fabric. table 4-6 ? serdes i/o port names and descriptions port name type description data / reference pads pcie_x_rxdp0 input receive data. serdes di fferential positive input for each lane. each serdesif consists of 4 rx signals. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_rxdp1 pcie_x_rxdp2 pcie_x_rxdp3 pcie_x_rxdn0 input receive data. serdes differential negative input for each lane. each serdesif consists of 4 rx signals. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_rxdn1 pcie_x_rxdn2 pcie_x_rxdn3 pcie_x_txdp0 output transmit data. serdes differential positive output for each lane. each serdesif consists of 4 tx signals. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_txdp1 pcie_x_txdp2 pcie_x_txdp3 pcie_x_txdn0 output transmit data. serdes di fferential negative output for each lane. each serdesif consists of 4 tx signals. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_txdn1 pcie_x_txdn2 pcie_x_txdn3 common i/o pads pe r serdes interface pcie_x_rextl reference external reference resistor connection to calibrate tx/rx termination value. each serdesif consists of 2 rext signals?one for lane0 and lane1, and another for lane2 and lane3. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_rextr pcie_x_refclk0p clock reference clock differential positive. each serdesif consists of two signals (refclk0_p, refclk1_p). these are dual purpose i/os; you can use these lines for msiod fabric, if serdesi f is not activated. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_refclk1p pcie_x_refclk0n clock reference clock differenti al negative. each serdesif consists of two signals (refclk0_p, refclk1_p). thes e are dual purpose i/os; you can use these lines for msiod fabric, if serd esif is not activated. here x = 0 for serdesif_0 and x = 1 for serdesif_1. if unused, can be left floating. pcie_x_refclk1n
smartfusion2 system-on-chip fpgas revision 0 4-9 jtag pins smartfusion2 devices have dedicated jtag pins in b ank 4. jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). the debug port is implemented using a serial wire jt ag debug port (swj-dp) rather than a serial wire debug port (sw-dp). this enables either the m3 jtag or the sw protocol to be used for debugging. table 4-7 ? jtag pin names and descriptions name type bus size description jtagsel in 1 jtag controller selection. depending on the state of the jtagsel pi n, an external jtag controller will see the fpga fabric tap/auxiliary t ap (high) or the cortex-m3 jtag debug interface (low). the jtagsel pin should be connected to an external pull-up resistor such that the default configuration selects the fpga fabric tap. jtag_tck/ m3_tck in 1 test clock. serial input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/pull-down resistor. if jtag is not used, microsemi recommends tying it off. connect tck to gnd or +3.3 v through a resistor placed close to the fpga pin. this prevents totem-pole current on the input buffer and operation in case tms enters an undesired state. note t hat to operate at all +3.3 v voltages, 500 ? to 1 k ? will satisfy the requirements. jtag_tdi/ m3_tdi in 1 test data. serial input for jtag boundary scan, isp, and ujtag usage. there is an internal weak pull-up resistor on the tdi pin. jtag_tdo/ m3_tdo/ m3_swo out 1 test data. serial output for jtag boundary scan, isp, and ujtag usage. the tdo pin does not have an internal pull-up/-down resistor. m3_swo: serial wire viewer output jtag_tms/ m3_tms/ m3_swdio 1 test mode select. the tms pin controls the use of the ieee1532 boundary scan pins (tck, tdi, tdo, and trst). there is an internal weak pull-up resistor on the tms pin. m3_swdio: serial wire debug data input/output jtag_trstb/ m3_trstb 1 boundary scan reset pin. the trst pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. if jtag is not used, an external pull-down resistor (1k) could be included to ensure the tap is held in reset mode. in critical applications, an upset in the jtag circuit could allo w entering an undesired jtag state. in such cases, microsemi recommends that you tie off trst to gnd through a resistor (1k) placed close to the fpga pin. the trstb pin also resets the serial wire jtag debug port (swj-d p) circuitry within the cortex-m3 processor.
pin descriptions 4-10 revision 0 microcontroller subsystem (mss) table 4-8 ? mss pin names and descriptions name type description inter-integrated circ uit (i2c) peripherals i2c_0_scl in/out i2c bus serial clock output. can also be used as an mss gpio or usb_data1_c or fabric i/o. i2c_0_sda in/out i2c bus serial data input/out put. can also be used as an mss gpio or usb_data0_c or fabric i/o. i2c_1_scl in/out i2c bus serial clock output. can also be used as an mss gpio or usb_data4_a. i2c_1_sda in/out i2c bus serial data input/out put. can also be used as an mss gpio or usb_data3_a. universal asynchronous receiver /transmitter (uart) peripherals mmuart_0_clk out uart clock. can also be used as an mss gpio or usb_nxt_c or fabric i/o. mmuart_0_txd out uart transmit data. can also be used as an mss gpio or usb_dir_c or fabric i/o. mmuart_0_rxd in uart receive data. can also be used as an mss gpio or usb_stp_c or fabric i/o. mmuart_0_cts in uart clear to send. can also be used as an mss gpio or usb_data7_c or fabric i/o. mmuart_0_rts out uart request to send. can also be used as an mss gpio or usb_data5_c or fabric i/o. mmuart_0_dtr out modem data terminal ready. can also be used as an mss gpio or usb_data6_c or fabric i/o. mmuart_0_dcd in modem data carrier detects. can also be used as an mss gpio or fabric i/o. mmuart_0_dsr in modem data set ready. can also be used as an mss gpio or fabric i/o. mmuart_0_ri in modem ring indicator. can also be used as an mss gpio or fabric i/o. mmuart_1_clk out uart clock. can also be used as an mss gpio or usb_data4_c. mmuart_1_txd out uart transmit data. can also be used as an mss gpio or usb_data2_c or fabric i/o. mmuart_1_rxd in uart receive data. can also be used as an mss gpio or usb_data3_c or fabric i/o. mmuart_1_cts in uart clear to send. can also be used as an mss gpio or fabric i/o. mmuart_1_rts out uart request to send. can also be used as an mss gpio or fabric i/o. mmuart_1_dtr out modem data terminal ready. can also be used as an mss gpio or fabric i/o.
smartfusion2 system-on-chip fpgas revision 0 4-11 mmuart_1_dcd in modem da ta carrier detects. can also be used as an mss gpio or fabric i/o. mmuart_1_dsr in modem data set ready. can also be used as an mss gpio or fabric i/o. mmuart_1_ri in modem ring indicator. can also be used as an mss gpio or fabric i/o. serial peripheral inte rface (spi) controllers spi_0_ss0 out spi slave select0. can also be used as an mss gpio or usb_nxt_a or fabric i/o. spi_0_ss1 out spi slave select1. can also be used as an mss gpio or usb_data5_a or fabric i/o. spi_0_ss2 out spi slave select2. can also be used as an mss gpio or usb_data6_a or fabric i/o. spi_0_ss3 out spi slave select3. can also be used as an mss gpio or usb_data7_a or fabric i/o. spi_0_ss4 out spi slave select4. can also be used as an mss gpio or fabric i/o. spi_0_ss5 out spi slave select5. can also be used as an mss gpio or fabric i/o. spi_0_ss6 out spi slave select6. can also be used as an mss gpio or fabric i/o. spi_0_ss7 out spi slave select7. can also be used as an mss gpio or fabric i/o. spi_0_clk out spi clock. can also be used as an mss gpio or usb_xclk_a. spi_0_sdo out spi data output. can also be used as an mss gpio or usb_stp_a or fabric i/o. spi_0_sdi in spi data input. can also be used as an mss gpio or usb_dir_a or fabric i/o. spi_1_ss0 out spi slave select0. can also be used as an mss gpio or fabric i/o. spi_1_ss1 out spi slave select1. can also be used as an mss gpio or fabric i/o. spi_1_ss2 out spi slave select2. can also be used as an mss gpio or fabric i/o. spi_1_ss3 out spi slave select3. can also be used as an mss gpio or fabric i/o. spi_1_ss4 out spi slave select4. can also be used as an mss gpio or fabric i/o. table 4-8 ? mss pin names and descriptions (continued) name type description
pin descriptions 4-12 revision 0 multi-function i/os certain i/os can have more than one function. users select the functionality through libero configuration tools. the name of a pin shows the func tionalities for which that pin can be configured and used. example pin name: msio48nb1/i2c_0_scl/gpio_31_b/usb_data1_c this i/o port is multi-purpose and can be configured as msio, i2c0 clock, fabric i/o, or usb_data1_c. spi_1_ss5 out spi slave select5. can also be used as an mss gpio or fabric i/o. spi_1_ss6 out spi slave select6. can also be used as an mss gpio or fabric i/o. spi_1_ss7 out spi slave select7. can also be used as an mss gpio or fabric i/o. spi_1_clk out spi clock. can also be used as an mss gpio. spi_1_sdo out spi data output. can also be used as an mss gpio or fabric i/o. spi_1_sdi in spi data input. can also be used as an mss gpio or fabric i/o. table 4-8 ? mss pin names and descriptions (continued) name type description
smartfusion2 system-on-chip fpgas revision 0 4-13 pin assignment tables fg896 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pro ducts/solutions/package/docs.aspx . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak a1 ball pad corner
pin descriptions 4-14 revision 0 fg896 pin number m2s050t function a2 pcie_1_txdn0 a3 vss a4 pcie_1_txdn1 a5 vss a6 pcie_1_txdn2 a7 vss a8 pcie_1_txdn3 a9 ddrio91pb0/gb0/ccc_nw0_i3 a10 ddrio90pb0/mddr_dqs_ecc a11 ddrio88pb0/mddr_dq32_ecc a12 ddrio86pb0/mddr_dq0 a13 ddrio84pb0/mddr_dqs0 a14 ddrio83nb0/mddr_dq4 a15 ddrio80pb0/mddr_dq8 a16 ddrio78pb0/gb8/ccc_ne0_i3/mddr_dqs1 a17 ddrio76pb0/gb 12/ccc_ne1_i2/mddr_dq12 a18 ddrio74pb0/mddr_dq16 a19 ddrio72pb0/mddr_dqs2 a20 ddrio71nb0/mddr_dq20 a21 ddrio68pb0/mddr_dq24 a22 ddrio66nb0/mddr_dqs3_n a23 ddrio64pb0/mddr_dq28 a24 ddrio60pb0/mddr_rst_n a25 ddrio59pb0/mddr_clk a26 ddrio57pb0/mddr_ba2 a27 ddrio55pb0/mddr_addr3 a28 ddrio55nb0/mddr_addr4 a29 vss aa1 msiod134nb7 aa2 msiod134pb7 aa3 msiod129nb7 aa4 msiod136nb7 aa5 msiod141nb7 aa6 pcie_0_rextl aa7 pll_pcie_0_vssa aa8 pll_pcie_0_vdda
smartfusion2 system-on-chip fpgas revision 0 4-15 aa9 pcie_0_rextr aa10 pll4_vssa aa11 pcie0vddiol aa12 pcie0vddior aa13 vddi5 aa14 vddi5 aa15 vddi5 aa16 vddi5 aa17 vddi5 aa18 vddi5 aa19 vddi5 aa20 vddi5 aa21 vdd aa22 vss aa23 pll_fddr_vssa aa24 vddi4 aa25 jtagsel aa26 msio2pb3/usb_stp_b aa27 msio2nb3/usb_nxt_b aa28 msio7nb3/can_tx/g pio_2_a/usb_data0_a aa29 msio8nb3/can_tx_en_ n/gpio_4_a/usb_data2_a aa30 sc_spi_clk ab1 msiod135nb7 ab2 msiod135pb7 ab3 vddi7 ab4 msiod137nb7 ab5 pcie0vdd ab6 vss ab7 vss ab8 pcie_0_rxdp0 ab9 pcie_0_rxdn0 ab10 pcie_0_rxdp2 ab11 pcie_0_rxdn2 ab12 pcie0vdd ab13 vss ab14 vss fg896 pin number m2s050t function
pin descriptions 4-16 revision 0 ab15 vss ab16 vss ab17 vss ab18 vss ab19 vss ab20 vref5 ab21 xtlosc ab22 extlosc ab23 pll_fddr_vdda ab24 vss ab25 jtag_trstb/m3_trstb ab26 msio0nb3/usb_data7_b ab27 jtag_tms/m3_tms/m3_swdio ab28 vss ab29 msio6pb3/usb_data6_b ab30 msio6nb3 ac1 msiod138nb7 ac2 msiod138pb7 ac3 msiod140nb7 ac4 msiod143pb7 ac5 vss ac6 vss ac7 pcie0vddplll ac8 pcie0pllrefretl ac9 pcie_0_rxdp1 ac10 pcie_0_rxdn1 ac11 vpp ac12 vss ac13 vdd ac14 vdd ac15 vdd ac16 vdd ac17 vdd ac18 vdd ac19 vdd ac20 vss fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-17 ac21 vss ac22 vss ac23 vss ac24 vddi4 ac25 jtag_tdo/m3_tdo/m3_swo ac26 jtag_tck/m3_tck ac27 devrst_n ac28 msio1pb3/usb_xclk_b ac29 msio1nb3/usb_dir_b ac30 msio5nb3/usb_data5_b ad1 msiod139nb7 ad2 msiod139pb7 ad3 msiod143nb7 ad4 vss ad5 vss ad6 vss ad7 vss ad8 vss ad9 pcie0pllrefretr ad10 pcie_0_rxdp3 ad11 pcie_0_rxdn3 ad12 ddrio150pb5/fddr_fifo_we_in_ecc ad13 vref5 ad14 vss ad15 vss ad16 vref5 ad17 vss ad18 vss ad19 vss ad20 vss ad21 vss ad22 vss ad23 vss ad24 vss ad25 vss ad26 vss fg896 pin number m2s050t function
pin descriptions 4-18 revision 0 ad27 vss ad28 vss ad29 vss ad30 msio5pb3/usb_data4_b ae1 msiod146nb6/pcie_0_refclk1n ae2 msiod144nb7 ae3 vss ae4 vss ae5 vss ae6 vss ae7 vss ae8 vss ae9 pcie0vddpllr ae10 vddi5 ae11 ddrio147pb5/fddr_fifo_we_out_ecc ae12 vss ae13 vddi5 ae14 ddrio158nb5/f ddr_fifo_we_out1 ae15 ddrio162pb5/fddr_fifo_we_in1 ae16 vddi5 ae17 vss ae18 ddrio170nb5/f ddr_fifo_we_out3 ae19 vddi5 ae20 vss ae21 ddrio174pb5/fddr_fifo_we_in3 ae22 vddi5 ae23 ddrio185nb5/fddr_addr6 ae24 ddrio185pb5/fddr_addr5 ae25 vddi5 ae26 vss ae27 ddrio189pb5/fddr_addr12 ae28 vddi5 ae29 ddrio178nb5/fddr_cs_n ae30 msio4nb3/usb_data3_b af1 msiod146pb6/pcie_0_refclk1p af2 vss fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-19 af3 vss af4 vss af5 vss af6 vss af7 vss af8 vss af9 fddr_imp_calib_ecc af10 vddi5 af11 ddrio152pb5/gb3/ccc_sw0_i3/fddr_dq34_ecc af12 ddrio154nb5/fddr_dq3 af13 vddi5 af14 ddrio157nb5/fddr_dq6 af15 ddrio160nb5/fddr_dq11 af16 vddi5 af17 ddrio164pb5/vccc_se1/fddr_dq14 af18 ddrio166nb5/fddr_dq19 af19 vddi5 af20 ddrio169nb5/fddr_dq22 af21 ddrio172nb5/fddr_dq27 af22 vddi5 af23 ddrio176pb5/fddr_dq30 af24 ddrio186nb5/fddr_addr7 af25 ddrio186pb5/fddr_odt af26 vss af27 ddrio189nb5/fddr_addr13 af28 vddi5 af29 ddrio178pb5/fddr_cke af30 vss ag1 vss ag2 vss ag3 vss ag4 vss ag5 vss ag6 vss ag7 vss ag8 vss fg896 pin number m2s050t function
pin descriptions 4-20 revision 0 ag9 ddrio147nb5/ccc_sw0_i2 ag10 ddrio150nb5/fddr_dm_rdqs4_ecc ag11 ddrio152nb5/gb7/ccc_sw1_i2/fddr_dq35_ecc ag12 ddrio154pb5/fddr_dq2 ag13 ddrio156pb5/fddr_dm_rqds0 ag14 ddrio157pb5/fddr_dq5 ag15 ddrio160pb5/vccc_se0/fddr_dq10 ag16 ddrio162nb5/fddr_dm_rqds1 ag17 ddrio164nb5/fddr_dq15 ag18 ddrio166pb5/fddr_dq18 ag19 ddrio168pb5/fddr_dm_rqds2 ag20 ddrio169pb5/fddr_dq21 ag21 ddrio172pb5/fddr_dq26 ag22 ddrio174nb5/fddr_dm_rqds3 ag23 ddrio176nb5/fddr_dq31 ag24 ddrio181pb5/fddr_ba0 ag25 ddrio181nb5/fddr_ba1 ag26 vddi5 ag27 ddrio187pb5/fddr_addr8 ag28 ddrio187nb5/fddr_addr9 ag29 ddrio190pb5/fddr_addr14 ag30 ddrio177pb5/fddr_ras_n ah1 vss ah2 vss ah3 vss ah4 vss ah5 vss ah6 vss ah7 vss ah8 vss ah9 vss ah10 vddi5 ah11 vss ah12 vss ah13 vddi5 ah14 vss fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-21 ah15 vss ah16 vddi5 ah17 vss ah18 vss ah19 vddi5 ah20 vss ah21 vss ah22 vddi5 ah23 vss ah24 vss ah25 vddi5 ah26 vss ah27 ddrio183pb5/fddr_addr1 ah28 vddi5 ah29 ddrio190nb5/fddr_addr15 ah30 ddrio177nb5/fddr_we_n aj1 vss aj2 pcie_0_txdp0 aj3 vss aj4 pcie_0_txdp1 aj5 vss aj6 pcie_0_txdp2 aj7 vss aj8 pcie_0_txdp3 aj9 ddrio148nb5/probe_b aj10 ddrio149nb5/fddr_dqs_ecc_n aj11 ddrio151nb5/fddr_dq33_ecc aj12 ddrio153nb5/fddr_dq1 aj13 ddrio155nb5/fddr_dqs0_n aj14 ddrio158pb5/fddr_dq7 aj15 ddrio159nb5/fddr_dq9 aj16 ddrio161nb5/fddr_dqs1_n aj17 ddrio163nb5/fddr_dq13 aj18 ddrio165nb5/fddr_dq17 aj19 ddrio167nb5/fddr_dqs2_n aj20 ddrio170pb5/fddr_dq23 fg896 pin number m2s050t function
pin descriptions 4-22 revision 0 aj21 ddrio171nb5/fddr_dq25 aj22 ddrio173pb5/fddr_dqs3 aj23 ddrio175nb5/fddr_dq29 aj24 ddrio179nb5/fddr_cas_n aj25 ddrio180nb5/fddr_clk_n aj26 ddrio182nb5/fddr_addr0 aj27 ddrio183nb5/fddr_addr2 aj28 ddrio188nb5/fddr_addr11 aj29 ddrio188pb5/fddr_addr10 aj30 vss ak2 pcie_0_txdn0 ak3 vss ak4 pcie_0_txdn1 ak5 vss ak6 pcie_0_txdn2 ak7 vss ak8 pcie_0_txdn3 ak9 ddrio148pb5/probe_a ak10 ddrio149pb5/fddr_dqs_ecc ak11 ddrio151pb5/fddr_dq32_ecc ak12 ddrio153pb5/fddr_dq0 ak13 ddrio155pb5/fddr_dqs0 ak14 ddrio156nb5/fddr_dq4 ak15 ddrio159pb5/ccc_sw1_i3/fddr_dq8 ak16 ddrio161pb5/gb11/vccc_se0/fddr_dqs1 ak17 ddrio163pb5/gb15/vccc_se1/fddr_dq12 ak18 ddrio165pb5/fddr_dq16 ak19 ddrio167pb5/fddr_dqs2 ak20 ddrio168nb5/fddr_dq20 ak21 ddrio171pb5/fddr_dq24 ak22 ddrio173nb5/fddr_dqs3_n ak23 ddrio175pb5/fddr_dq28 ak24 ddrio179pb5/fddr_rst_n ak25 ddrio180pb5/fddr_clk ak26 ddrio182pb5/fddr_ba2 ak27 ddrio184pb5/fddr_addr3 fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-23 ak28 ddrio184nb5/fddr_addr4 ak29 vss b1 vss b2 pcie_1_txdp0 b3 vss b4 pcie_1_txdp1 b5 vss b6 pcie_1_txdp2 b7 vss b8 pcie_1_txdp3 b9 ddrio91nb0/gb4/ccc_nw1_i2 b10 ddrio90nb0/mddr_dqs_ecc_n b11 ddrio88nb0/mddr_dq33_ecc b12 ddrio86nb0/mddr_dq1 b13 ddrio84nb0/mddr_dqs0_n b14 ddrio81pb0/mddr_dq7 b15 ddrio80nb0/mddr_dq9 b16 ddrio78nb0/mddr_dqs1_n b17 ddrio76nb0/mddr_dq13 b18 ddrio74nb0/mddr_dq17 b19 ddrio72nb0/mddr_dqs2_n b20 ddrio69pb0/mddr_dq23 b21 ddrio68nb0/mddr_dq25 b22 ddrio66pb0/mddr_dqs3 b23 ddrio64nb0/mddr_dq29 b24 ddrio60nb0/mddr_cas_n b25 ddrio59nb0/mddr_clk_n b26 ddrio57nb0/mddr_addr0 b27 ddrio56nb0/mddr_addr2 b28 ddrio51nb0/mddr_addr11 b29 ddrio51pb0/mddr_addr10 b30 vss c1 vss c2 vss c3 vss c4 vss fg896 pin number m2s050t function
pin descriptions 4-24 revision 0 c5 vss c6 vss c7 vss c8 vss c9 vss c10 vddi0 c11 vss c12 vss c13 vddi0 c14 vss c15 vss c16 vddi0 c17 vss c18 vss c19 vddi0 c20 vss c21 vss c22 vddi0 c23 vss c24 vss c25 vddi0 c26 vss c27 ddrio56pb0/mddr_addr1 c28 vddi0 c29 ddrio49nb0/mddr_addr15 c30 ddrio62nb0/mddr_we_n d1 vss d2 vss d3 vss d4 vss d5 vss d6 vss d7 vss d8 vss d9 ddrio92nb0/ccc_nw0_i2 d10 ddrio89nb0/mddr_dm_rqds4_ecc fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-25 d11 ddrio87nb0/mddr_dq35_ecc d12 ddrio85pb0/mddr_dq2 d13 ddrio83pb0/mddr_dm_rqds0 d14 ddrio82pb0/mddr_dq5 d15 ddrio79pb0/ccc_ne0_i2/mddr_dq10 d16 ddrio77nb0/mddr_dm_rqds1 d17 ddrio75nb0/mddr_dq15 d18 ddrio73pb0/mddr_dq18 d19 ddrio71pb0/mddr_dm_rqds2 d20 ddrio70pb0/mddr_dq21 d21 ddrio67pb0/mddr_dq26 d22 ddrio65nb0/mddr_dm_rqds3 d23 ddrio63nb0/mddr_dq31 d24 ddrio58pb0/mddr_ba0 d25 ddrio58nb0/mddr_ba1 d26 vddi0 d27 ddrio52pb0/mddr_addr8 d28 ddrio52nb0/mddr_addr9 d29 ddrio49pb0/mddr_addr14 d30 ddrio62pb0/mddr_ras_n e1 msiod94nb9/pcie_1_refclk0n e2 vss e3 vss e4 vss e5 vss e6 vss e7 vss e8 vss e9 mddr_imp_calib_ecc e10 vddi0 e11 ddrio87pb0/ccc_nw1_i3/mddr_dq34_ecc e12 ddrio85nb0/mddr_dq3 e13 vddi0 e14 ddrio82nb0/mddr_dq6 e15 ddrio79nb0/mddr_dq11 e16 vddi0 fg896 pin number m2s050t function
pin descriptions 4-26 revision 0 e17 ddrio75pb0/ccc_ne1_i3/mddr_dq14 e18 ddrio73nb0/mddr_dq19 e19 vddi0 e20 ddrio70nb0/mddr_dq22 e21 ddrio67nb0/mddr_dq27 e22 vddi0 e23 ddrio63pb0/mddr_dq30 e24 ddrio53nb0/mddr_addr7 e25 ddrio53pb0/mddr_odt e26 vss e27 ddrio50nb0/mddr_addr13 e28 vddi0 e29 ddrio61pb0/mddr_cke e30 vss f1 msiod94pb9/pcie_1_refclk0p f2 msio108nb8 f3 vss f4 vss f5 vss f6 vss f7 vss f8 vss f9 pcie1vddpllr f10 vddi0 f11 ddrio92pb0/mddr_fifo_we_out_ecc f12 vss f13 vddi0 f14 ddrio81nb0/mddr_fifo_we_out1 f15 ddrio77pb0/mddr_fifo_we_in1 f16 vddi0 f17 vss f18 ddrio69nb0/mddr_fifo_we_out3 f19 vddi0 f20 vss f21 ddrio65pb0/mddr_fifo_we_in3 f22 vddi0 fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-27 f23 ddrio54nb0/mddr_addr6 f24 ddrio54pb0/mddr_addr5 f25 vss f26 vddi0 f27 ddrio50pb0/mddr_addr12 f28 vddi0 f29 ddrio61nb0/mddr_cs_n f30 msio45nb1/mmuart_0_dcd/gpio_22_b g1 msio100nb8 g2 msio95pb8 g3 msio95nb8 g4 vss g5 vss g6 vss g7 vss g8 vss g9 pcie1pllrefretr g10 pcie_1_rxdp3 g11 pcie_1_rxdn3 g12 ddrio89pb0/mddr_fifo_we_in_ecc g13 vref0 g14 vss g15 vss g16 vref0 g17 vss g18 vss g19 vss g20 vss g21 vss g22 vss g23 vss g24 vss g25 vss g26 vss g27 vss g28 flash_golden fg896 pin number m2s050t function
pin descriptions 4-28 revision 0 g29 msio42nb1/mmuart_1_rxd/gpio_26_b/usb_data3_c g30 msio45pb1/mmu art_0_ri/gpio_21_b h1 msio99pb8 h2 msio99nb8 h3 vddi8 h4 msio96nb8 h5 vss h6 vss h7 pcie1vddplll h8 pcie1pllrefretl h9 pcie_1_rxdp1 h10 pcie_1_rxdn1 h11 vss h12 vss h13 vdd h14 vdd h15 vdd h16 vdd h17 vdd h18 vdd h19 vdd h20 vss h21 vss h22 vss h23 vss h24 pll0_vdda h25 pll0_vssa h26 msio47nb1/mmuart_ 0_clk/gpio_29_b/usb_nxt_c h27 msio46nb1/mmuart_0_txd/gpio_27_b/usb_dir_c h28 msio40nb1/mmuart_1_dcd/gpio_16_b h29 msio42pb1/gb14/vccc_se1/mmu art_1_clk/gpio_25_b/usb_data4_c h30 msio41nb1/mmuart_1_txd/gpio_24_b/usb_data2_c j1 msio102pb8 j2 msio102nb8 j3 msio98pb8 j4 msio98nb8 fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-29 j5 vss j6 vss j7 vss j8 pcie_1_rxdp0 j9 pcie_1_rxdn0 j10 pcie_1_rxdp2 j11 pcie_1_rxdn2 j12 pcie1vdd j13 vss j14 vss j15 vss j16 vss j17 vss j18 vss j19 vss j20 vref0 j21 vss j22 pll_mddr_vdda j23 pll_mddr_vssa j24 pll1_vssa j25 pll1_vdda j26 msio43nb1/mmuart_0_dtr/gpio_18_b/usb_data6_c j27 msio35nb2/gpio_6_b j28 msio38nb1/mmuart_1_dtr/gpio_12_b j29 msio38pb1/mmuar t_1_rts/gpio_11_b j30 msio41pb1/gb10/ vccc_se0/usb_xclk_c k1 vss k2 vddi8 k3 msio101nb8 k4 vss k5 msio97nb8 k6 pcie_1_rextl k7 pll_pcie_1_vssa k8 pll_pcie_1_vdda k9 pcie_1_rextr k10 pll3_vdda fg896 pin number m2s050t function
pin descriptions 4-30 revision 0 k11 pcie1vddiol k12 pcie1vddior k13 vddi0 k14 vddi0 k15 vddi0 k16 vddi0 k17 vddi0 k18 vddi0 k19 vddi0 k20 vddi0 k21 vdd k22 vss k23 msio48pb1/i2c_0_sda/gpio_30_b/usb_data0_c k24 msio48nb1/i2c_0_sc l/gpio_31_b/usb_data1_c k25 msio44nb1/mmuart_0_dsr/gpio_20_b k26 vddi1 k27 vss k28 msio34nb2/gpio_4_b k29 msio37n b2/gpio_10_b k30 msio37pb2/gpio_9_b l1 msio104nb8 l2 msio103pb8 l3 msio103nb8 l4 msio113nb8 l5 vss l6 msiod93pb9/pcie_1_refclk1p l7 msiod93nb9/pcie_1_refclk1n l8 pcie1vdd l9 pll2_vssa l10 pll3_vssa l11 vss l12 vss l13 vss l14 vss l15 vss l16 vss fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-31 l17 vss l18 vss l19 vss l20 vss l21 vddi1 l22 vdd l23 msio47pb1/mmuart_0_rxd/gpio_28_b/usb_stp_c l24 vss l25 vddi1 l26 msio39nb1/mmuart_1_dsr/gpio_14_b l27 vddi2 l28 msio34pb2/gpio_3_b l29 msio33nb2/gpio_2_b l30 msio33pb2/gpio_1_b m1 msio107pb8 m2 msio107nb8 m3 msio106pb8 m4 msio106nb8 m5 05nb8 m6 vddi8 m7 vddi9 m8 msio97pb8 m9 pll2_vdda m10 vdd m11 vss m12 vss m13 vss m14 vss m15 vss m16 vss m17 vss m18 vss m19 vss m20 vss m21 vss m22 vss fg896 pin number m2s050t function
pin descriptions 4-32 revision 0 m23 msio44pb1/mmuart_0_cts/gpio_19_b/usb_data7_c m24 msio43pb1/mmuart_0_ rts/gpio_17_b/usb_data5_c m25 msio40pb1/ccc_ne1_i 1/mmuart_1_ri/gpio_15_b m26 msio36nb2/gpio_8_b m27 msio32nb2/gpio_0_b m28 msio30nb2/usb_data7_d/gpio_23_b m29 vss m30 msio29nb2/usb_data5_d n1 msio111pb8 n2 msio111nb8 n3 msio110pb8 n4 msio110nb8 n5 msio109nb8 n6 msio100pb8 n7 msio96pb8 n8 msio101pb8 n9 msio104pb8 n10 vddi8 n11 vss n12 vss n13 vss n14 vss n15 vss n16 vss n17 vss n18 vss n19 vss n20 vss n21 vddi1 n22 vdd n23 msio39pb1/ccc_ne0_i 1/mmuart_1_cts/gpio_13_b n24 msio36pb2/gpio_7_b n25 msio35pb2/gpio_5_b n26 msio31nb2/gpio_30_a n27 msio30pb2/usb_data6_d n28 msio29pb2/usb_data4_d fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-33 n29 msio28nb2/usb_data3_d n30 msio26nb2/usb_nxt_d p1 msio115pb8/gb2/ccc_nw0_i1 p2 msio115nb8 p3 msio114pb8/gb6/ccc_nw1_i1 p4 msio114nb8 p5 msio112nb8 p6 msio105pb8 p7 msio108pb8 p8 msio112pb8 p9 msio116pb8/ccc_nw1_i0 p10 vdd p11 vss p12 vss p13 vss p14 vss p15 vss p16 vss p17 vss p18 vss p19 vss p20 vss p21 vddi2 p22 vss p23 msio32 pb2/gpio_31_a p24 msio31 pb2/gpio_29_a p25 msio28pb2/usb_data2_d p26 msio27pb2/usb_data0_d p27 msio27nb2/usb_data1_d p28 msio26pb2/usb_stp_d p29 msio25nb2/usb_dir_d p30 msio25pb2/usb_xclk_d r1 msiod119pb7/gb1/ccc_sw0_i1 r2 msiod119nb7 r3 msiod118pb7/gb5/ccc_sw1_i1 r4 msiod118nb7 fg896 pin number m2s050t function
pin descriptions 4-34 revision 0 r5 msio116nb8 r6 msio117nb8 r7 msio109pb8 r8 msio113pb8 r9 msio117pb8/ccc_nw0_i0 r10 vddi8 r11 vss r12 vss r13 vss r14 vss r15 vss r16 vss r17 vss r18 vss r19 vss r20 vss r21 vddi2 r22 vdd r23 vpp r24 msio24pb3/spi_1_ss2/gpio_15_a r25 msio23pb3/spi_0_ss3/gpio_10_a/usb_data7_a r26 vddi2 r27 vss r28 msio24nb3/spi_1_ss3/gpio_16_a r29 msio23nb3/spi_1_ss1/gpio_14_a r30 msio22nb3/spi_0_ ss2/gpio_9_a/usb_data6_a t1 msiod120nb7 t2 vss t3 vddi7 t4 msiod121nb7 t5 msiod125nb7 t6 msiod128pb7 t7 msiod120pb7/ccc_sw1_i0 t8 msiod124pb7 t9 msiod133pb7 t10 vdd fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-35 t11 vss t12 vss t13 vss t14 vss t15 vss t16 vss t17 vss t18 vss t19 vss t20 vss t21 vss t22 vss t23 vssnvm t24 msio20pb3/gb9/vccc_se0/gpio_25_a t25 vddi3 t26 msio21pb3/gpio_27_a t27 msio21nb3/gpio_28_a t28 msio20nb3/gb13/vccc_se1/gpio_26_a t29 vppnvm t30 msio22pb3/spi_0_ ss1/gpio_8_a/usb_data5_a u1 msiod122nb7 u2 msiod122pb7 u3 msiod123nb7 u4 msiod123pb7 u6 msiod136pb7 u7 msiod121pb7/ccc_sw0_i0 u8 msiod125pb7 u9 msiod132pb7 u10 vddi7 u11 vss u12 vss u13 vss u14 vss u15 vss u16 vss u17 vss fg896 pin number m2s050t function
pin descriptions 4-36 revision 0 u18 vss u19 vss u20 vss u21 vddi3 u22 vdd u23 msio16pb3/spi_1_clk u24 msio15pb3/spi_0_ss6/gpio_21_a u25 msio19pb3/spi_1_ss6/gpio_23_a u26 msio15nb3/spi_0_ss7/gpio_22_a u27 msio16nb3/spi_1_sdi/gpio_11_a u28 vddi3 u29 vss u30 msio19nb3/spi_1_ss7/gpio_24_a v1 msiod127pb7 v2 msiod127nb7 v3 msiod126nb7 v4 msiod126pb7 v5 msiod130pb7 v6 msiod129pb7 v7 msiod144pb7 v8 msiod140pb7 v9 msiod145pb6/pcie_0_refclk0p v10 msiod145nb6/pcie_0_refclk0n v11 vss v12 vss v13 vss v14 vss v15 vss v16 vss v17 vss v18 vss v19 vss v20 vss v21 vss v22 msio12pb3/spi_0_clk/usb_xclk_a v23 msio11pb3/ccc _ne0_i0/i2c_1_sda/gpio_0_a/usb_data3_a fg896 pin number m2s050t function
smartfusion2 system-on-chip fpgas revision 0 4-37 v24 msio8pb3/can_rx/g pio_3_a/usb_data1_a v25 vpp v26 msio11nb3/ccc_ne1_i0/i2c_1_scl/gpio_1_a/usb_data4_a v27 msio17pb3/ spi_1_sdo/gpio_12_a v28 msio17nb3/ spi_1_ss0/gpio_13_a v29 msio18pb3/ spi_1_ss4/gpio_17_a v30 msio18nb3/ spi_1_ss5/gpio_18_a w1 msiod128nb7 w2 vss w3 vddi7 w4 msiod132nb7 w5 msiod130nb7 w6 msiod133nb7 w7 msiod141pb7 w8 msiod137pb7 w9 vddi6 w10 vddi7 w11 vss w12 vss w13 vss w14 vss w15 vss w16 vss w17 vss w18 vss w19 vss w20 vss w21 vddi3 w22 vdd w23 msio7pb3 w24 msio3pb3/usb_data0_b w25 msio4pb3/usb_data2_b w26 sc_spi_ss w27 msio13pb3/spi_0_sdo/gpio_6_a/usb_stp_a w28 msio13nb3/spi_0_ss0 /gpio_7_a/usb_nxt_a w29 msio14pb3/spi_0_ss4/gpio_19_a fg896 pin number m2s050t function
pin descriptions 4-38 revision 0 w30 msio14nb3/spi_0_ss5/gpio_20_a y1 msiod131nb7 y2 msiod131pb7 y3 vddi7 y4 vss y5 vss y6 msiod142nb7 y7 msiod142pb7 y8 pll5_vssa y9 pll4_vdda y10 pll5_vdda y11 vss y12 vss y13 vss y14 vss y15 vss y16 vss y17 vss y18 vss y19 vss y20 vss y21 vddi4 y22 msio0pb3 y23 jtag_tdi/m3_tdi y24 vpp y25 msio3nb3/usb_data1_b y26 vddi3 y27 vss y28 sc_spi_sdi y29 sc_spi_sdo y30 msio12nb3/spi_0_s di/gpio_5_a/ usb_dir_a fg896 pin number m2s050t function
revision 0 5-1 5 ? datasheet information datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "smartfusion2 device status" table on page vi , is designated as ei ther "product brief," "advance," "preliminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.
51700115-0/10.12 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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